Graphene Interconnect Structure for Lower Contact Resistance
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Solution Overview
Problem
As semiconductor devices downscale, the increasing contact resistance due to longer contact lengths between wirings hinders high integration and low power consumption, necessitating improved materials and structures for wiring lines.
Innovation Solution
The semiconductor device incorporates a protective film structure with graphene films on wiring lines, including side wall and bottom graphene films, and insulating capping films to reduce resistance and enhance performance, with varying thicknesses of these films optimized for different levels of metal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the feature size of semiconductor devices is decreased to achieve high integration, then the contact length between wirings increases, but the contact resistance increases
Solution Approach 1:
The patent changes the material parameter of the wiring line from conventional metals to graphene, which has fundamentally different electrical properties including higher electron mobility and lower resistivity. This material parameter change enables reduced contact resistance despite increased contact length due to device downscaling
Solution Approach 2:
The patent employs a composite structure consisting of graphene as the core wiring material combined with metal contact materials. This composite approach leverages the high electron mobility of graphene while maintaining compatibility with existing metal interconnect structures, thereby reducing contact resistance in scaled devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces contact resistance and improves the performance and reliability of semiconductor devices by minimizing electron collisions and enhancing the adhesive properties and crystal grain size of metal materials, thus supporting high integration and low power consumption.
Implementation Method 1
graphene films on wiring lines... to reduce resistance... by minimizing electron collisions
Implementation Method 2
enhancing the adhesive properties and crystal grain size of metal materials
Implementation Method 3
a first side wall graphene film extending along a side wall of the first line wiring
Data Source
AI summary
A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.


