Graphene Devices in Semiconductor Interconnect Structures
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher densities and smaller feature sizes in integrated circuits, which are limited by the performance of traditional silicon-based transistors, necessitating the exploration of alternative materials like graphene for enhanced performance and functionality in interconnect structures.
Innovation Solution
A semiconductor structure and circuit design that incorporates a graphene-based device within the interconnect levels, featuring a dielectric material layer and conductive regions, allowing for the integration of active devices and improved performance through the use of a graphene layer in contact with conductive elements and covered by additional dielectric and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional silicon-based transistors are used for downscaling, then manufacturing process control is simplified, but device performance and density are limited
Solution Approach 1:
The patent changes the material parameter from traditional silicon to graphene, which has superior electrical properties including higher electron mobility and saturation velocity. This parameter change enables devices to maintain or improve performance at smaller dimensions where silicon would fail, thus resolving the contradiction between density and performance limits
Solution Approach 2:
The patent creates a composite structure integrating graphene channels with silicon-based CMOS circuitry. The graphene devices are embedded within conventional interconnect structures, combining the high-density advantage of graphene with the mature manufacturing capabilities of silicon, thereby achieving both high density and reliable performance
2Productivity
If graphene-based devices are integrated into interconnect structures, then device performance and functionality are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent designs the interconnect structure to serve multiple functions: it provides electrical connectivity between devices while simultaneously serving as the substrate and support structure for graphene devices. The same dielectric layers and conductive regions that form interconnects also provide mechanical support and electrical contacts for the graphene channels, gates, and contacts, thereby reducing overall manufacturing complexity
Solution Approach 2:
The patent performs preliminary actions by first forming the complete interconnect structure with all dielectric and conductive layers before integrating the graphene devices. The interconnect structure is prepared in advance with pre-formed vias, trenches, and contact regions that are later filled or modified to accommodate graphene devices, simplifying the integration process
Data Source
AI summary
A graphene layer is provided onto at least an upper surface of a first dielectric material which includes at least one first conductive region contained therein. At least one semiconductor device is formed using the graphene layer as an element of the at least one semiconductor device. After forming the at least one semiconductor device, a second dielectric material is formed covering the graphene layer, the at least one semiconductor device, and portions of the first dielectric material. The second dielectric that is formed includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one semiconductor device.