Graphene Interconnect Edge Area Reduction Electrical Resistance
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Solution Overview
Problem
Graphene sheets for low-resistance interconnects in semiconductor devices face challenges in achieving low electrical resistance due to limited edge formation, which is crucial for efficient conduction, as existing methods do not effectively utilize the low-resistance properties of graphene edges.
Innovation Solution
A semiconductor device structure featuring a catalyst layer with side graphene layers and an upper graphene layer, where the side graphene layers have non-contacting edges that increase the edge area, reducing electrical resistance, and a manufacturing process that forms multiple edges on the graphene sheets to enhance conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional graphene sheets are used without multiple edges, then the structure is simple, but the electrical resistance is high due to limited edge formation
Solution Approach 1:
The graphene layer is segmented into multiple edge portions by forming catalyst layer patterns with different shapes (circular, rectangular, triangular) and stacking multiple catalyst layers. This segmentation creates multiple edges on the graphene sheet, increasing the edge area and reducing electrical resistance while maintaining manageable structural complexity through systematic patterning processes
2Reliability
If the graphene layer height is increased to improve adhesion, then adhesion is enhanced, but the electrical resistance increases due to reduced edge effectiveness
Solution Approach 1:
Instead of increasing the height (vertical dimension) of the graphene layer to improve adhesion, the invention creates multiple edges by patterning the catalyst layer in planar dimensions and stacking catalyst layers. This approach enhances adhesion through increased edge area and electrical conduction through multiple edge paths without increasing graphene layer height, effectively utilizing dimensional transformation to resolve the contradiction
3Reliability
If multiple catalyst layers are stacked to form multiple edges, then the edge area increases reducing electrical resistance, but the manufacturing process becomes more complex
Solution Approach 1:
The catalyst layer pattern formation process serves multiple functions: it defines the shape and position of catalyst layers, determines the edge configuration of graphene sheets, and enables stacking of multiple catalyst layers. This multi-functionality allows the same patterning process to create complex multi-edge structures without proportionally increasing manufacturing complexity, as the process achieves multiple objectives simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves lower electrical resistance compared to traditional graphene sheets without multiple edges, enabling efficient electrical conduction and reducing the height of the graphene layer, while the manufacturing process ensures uniform growth and adhesion, enhancing the performance of graphene interconnects.
Implementation Method 1
A graphene sheet is formed on an exposed face of a catalyst layer by CVD or the like
Implementation Method 2
Graphene sheets are a novel carbon material exhibiting quantized conduction (ballistic conduction) in the same manner as carbon nanotubes
Data Source
AI summary
According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.