Graphene Interconnect Structure for Low-Resistance Nano Wires
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Solution Overview
Problem
The challenge in semiconductor device interconnects is the formation of nano-scale wires with low resistance and minimal misalignment, as the resistivity of wire materials increases with decreasing line widths, making it difficult to achieve fine line widths without significant resistance increases.
Innovation Solution
An interconnect structure is developed with a first dielectric layer having a trench, a first conductive layer comprising stacked graphene layers within the trench, and a second conductive layer in a through hole extending through dielectric layers, utilizing graphene layers to reduce resistivity and prevent misalignment during the photolithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the line width of wires is decreased to achieve higher integration, then the size of semiconductor devices is reduced, but the resistivity of wire material increases rapidly
Solution Approach 1:
The patent employs a composite interconnect structure consisting of multiple materials: copper or cobalt as the base conductive material, graphene layers for resistivity reduction, and various dielectric materials (spin-on-glass, silicon oxide, silicon nitride) for insulation. This composite approach allows the system to achieve both small dimensions and low resistivity by combining the advantages of different materials.
Solution Approach 2:
The patent changes the physical and chemical parameters of the conductive material by incorporating graphene layers with specific properties (single-layer or multi-layer structures, controlled thickness) into the interconnect. This parameter modification reduces the resistivity of the wire material itself, allowing fine line widths to maintain low resistance.
2Manufacturing precision
If photolithography process is used for nano-patterning to form fine wires, then line widths can be reduced, but misalignment or overlay errors occur
Solution Approach 1:
The patent applies preliminary protective actions by forming low-k dielectric layers with specific etch selectivity before the patterning process. These layers serve as protective barriers and alignment references that prevent misalignment during subsequent photolithography and etching steps, ensuring accurate positioning of fine interconnect structures.
Solution Approach 2:
The patent introduces intermediary dielectric layers (spin-on-glass, silicon oxide) that act as mediators between different patterning steps. These intermediate layers provide a stable platform for alignment and serve as protective barriers, reducing the direct impact of photolithography misalignment on the final interconnect structure.
3Ease of manufacture
If conventional conductive materials are used in nano-scale wires, then material availability is ensured, but resistivity increases significantly at fine line widths
Solution Approach 1:
The patent creates a composite conductive system by combining conventional materials (copper, cobalt) with graphene layers. This composite structure maintains the ease of manufacturing associated with conventional materials while achieving the low resistivity properties needed for nano-scale interconnects. The graphene layers are integrated into existing fabrication processes.
Solution Approach 2:
The patent applies local quality enhancement by adding graphene layers specifically to the conductive pathways where resistivity is most critical, while maintaining conventional materials in other areas. This localized modification optimizes the resistivity of nano-scale wires without requiring complete material replacement throughout the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively reduces the increase in resistivity with decreasing line widths and minimizes misalignment, enabling the formation of wires with fine line widths, such as those less than 10 nm, while maintaining low resistance.
Implementation Method 1
a first conductive layer in the trench, the first conductive layer including a plurality of first graphene layers stacked in a direction from an inner surface of the trench toward a center of the trench
Data Source
AI summary
An interconnect structure may include a first dielectric layer including a trench, a first conductive layer in the trench and including a plurality of first graphene layers stacked in a direction from an inner surface of the trench toward a center of the trench, a second dielectric layer on the first dielectric layer and including a through hole extending to the trench, and a second conductive layer in the through hole.