Graphene Interconnect Formation in Polyimide ILD Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor interconnect fabrication processes face challenges with increasing resistance and capacitance issues due to material limitations, leading to reduced speed and power in integrated circuits, as well as increased signal crosstalk, which are not adequately addressed by existing technologies.
Innovation Solution
The use of a selective polyimide-to-graphene conversion process, where photosensitive or non-photosensitive polyimide dielectric layers are converted into graphene interconnect structures using light or laser exposure, eliminating the need for additional barrier layers and improving conductivity without high-temperature reactions or solvents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional copper interconnects are used in shrinking interconnect stacks, then interconnect fabrication can be performed with existing materials, but resistance and capacitance issues arise that adversely impact speed and power
Solution Approach 1:
The patent changes the material parameter from conventional copper interconnects to graphene interconnects, fundamentally altering the electrical properties. Graphene provides lower resistance and reduced parasitic capacitance, directly resolving the resistance and capacitance issues that limit speed and power in shrinking copper interconnect stacks
Solution Approach 2:
The patent employs a composite structure where graphene is integrated with polyimide dielectric layers. The graphene interconnects are formed within or on the polyimide matrix, creating a composite material system that combines the excellent electrical conductivity of graphene with the insulating and structural properties of polyimide, achieving both low resistance/capacitance and fabrication simplicity
2Productivity
If smaller spacing between interconnect geometries is implemented to accommodate dense circuitry, then circuit density increases, but parasitic capacitance increases which adversely impacts speed and power
Solution Approach 1:
The patent changes the interconnect material to graphene, which inherently possesses lower parasitic capacitance compared to copper. This material parameter change allows smaller spacing between interconnect geometries to be implemented without the parasitic capacitance penalty that would otherwise limit speed and power in high-density configurations
3Device complexity
If repetitive deposit, etch, plating and polishing steps are performed to form inter-level interconnect structures, then interconnect structures can be formed with multiple layers, but the process becomes complex, time-consuming and expensive
Solution Approach 1:
The patent employs a self-service mechanism where the polyimide dielectric layer serves dual purposes: it provides the insulating matrix and simultaneously serves as the precursor material for graphene formation. Through photodissociation and thermal treatment, the polyimide decomposes to form graphene interconnects in situ, eliminating the need for separate metal deposition, plating, and polishing steps that characterize conventional multi-layer interconnect fabrication
Solution Approach 2:
The patent utilizes phase transitions in the polyimide material to achieve graphene formation. The polyimide undergoes photodissociation upon light exposure, followed by thermal decomposition at elevated temperatures, transforming from a dielectric polymer phase to a conductive graphene phase. This phase transition mechanism enables the formation of graphene interconnects without requiring external metal deposition processes
4Speed
If higher performance demands require signals to operate at very high frequencies, then circuit performance improves, but increased parasitic capacitance causes signal crosstalk between adjacent conductors
Solution Approach 1:
The patent changes the interconnect material to graphene, which exhibits lower parasitic capacitance per unit length compared to copper. This parameter change reduces the capacitive coupling between adjacent high-frequency signal lines, thereby minimizing signal crosstalk while enabling higher operating frequencies and improved circuit performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances interconnect conductivity, reduces fabrication complexity and cost, and minimizes parasitic capacitance and signal crosstalk, thereby improving the electrical performance and reliability of integrated circuits.
Implementation Method 1
selectively applying irradiation from a light source to form a graphene interconnect structure in the one or more polymer ILD layers
Implementation Method 2
a laser light source may be selectively applied to directly convert one or more exposed portions of the non-photosensitive, carbon-containing polyimide dielectric layer into a graphene foam interconnect structure
Data Source
Figure 1~3
Figure 4~6
Figure 7~8
AI summary
A back-end-of-line integrated circuit is formed on an integrated circuit structure having one or more polymer interlayer dielectric (ILD) layers formed over a first conductive wiring line layer by selectively processing an exposed portion of the one or more polymer ILD layers with application irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer.