Graphene-Coated Interconnects With Air Gaps for Low Capacitance
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Solution Overview
Problem
The formation of metal oxide layers during subtractive reactive ion etching in integrated circuits increases interconnect resistance, and existing etching stop layers with high dielectric constants lead to parasitic capacitance and insufficient air gap volume in sub-20 nm pitches, affecting the performance of metal interconnects.
Innovation Solution
A hydrophobic graphene layer is selectively deposited on metal interconnect pillars to reduce metal oxide formation and act as a moisture barrier, enhancing conductivity and allowing sufficient air gap volume by using hydrogen reactants during deposition, thereby reducing parasitic capacitance and improving electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If subtractive reactive ion etching is used to form metal interconnects, then interconnect structures can be formed, but metal oxide layers form during the process which increases interconnect resistance
Solution Approach 1:
A graphene layer is deposited on the metal interconnect pillars before the subtractive reactive ion etching process. This pre-deposited graphene layer serves as a protective barrier that prevents metal oxide formation during the etching process, thereby maintaining low interconnect resistance and improving conductivity reliability.
Solution Approach 2:
The graphene layer acts as an intermediary protective layer between the metal interconnect material and the oxidizing environment during reactive ion etching. This intermediate graphene coating prevents direct oxidation of the metal while allowing the etching process to proceed, thus eliminating the harmful metal oxide formation that increases resistance.
2Manufacturing precision
If existing etching stop layers are used, then etching can be stopped at the desired depth, but these layers have high dielectric constants which lead to parasitic capacitance
Solution Approach 1:
The patent changes the dielectric parameter of the stop layer by using graphene, which has a low dielectric constant compared to traditional stop layer materials. This parameter change maintains the etching depth control function while significantly reducing the parasitic capacitance that would otherwise be generated by high-dielectric constant materials.
Solution Approach 2:
The graphene layer serves as a temporary protective and stopping layer during the etching process that can be easily removed or integrated into the final structure. It performs its function of controlling etching depth and preventing over-etching while contributing minimal parasitic capacitance due to its low dielectric constant.
3Manufacturing precision
If traditional dielectric materials are used in sub-20 nm pitches, then interconnect structures can be formed, but insufficient air gap volume is achieved which affects performance
Solution Approach 1:
The graphene coating on the metal interconnect pillars acts as a thin film that enables the formation of sufficient air gaps in sub-20 nm pitch structures. The thin graphene layer provides the necessary surface definition and protection while allowing adequate air gap volume to be maintained, which is critical for reducing parasitic capacitance and improving interconnect performance at advanced node dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The graphene layer effectively decreases metal oxide formation, reduces interconnect resistance, and provides a sufficient moisture barrier, allowing for efficient air gap formation and lower parasitic capacitance, thus enhancing the performance of metal interconnects in integrated circuits.
Implementation Method 1
graphene is difficult to work with, thus lessening its use. Some of the many benefits of graphene include a low dielectric constant, excellent moisture resistance with good Hydrophobic properties
Implementation Method 2
selectively depositing a graphene layer coating onto sidewalls of the first and second metal interconnect pillar structures
Implementation Method 3
selectively depositing a graphene layer coating onto sidewalls of the first and second metal interconnect pillar structures
Implementation Method 4
Air gaps within an integrated circuit fit this need, as air gaps have dielectric constants around 1 (humidity depending)
Data Source
AI summary
An integrated circuit configuration with graphene coated metal interconnect structures and airgap structures between the graphene coated metal interconnect structures and method for fabrication of the integrated circuit configuration may be provided. The structure may include a metal interconnect structure in contact with an electrode upon a substrate fabricated through subtractive metal reactive ion etching. The metal interconnect structure may have a thin coating of hydrophobic graphene surrounding the exterior of the metal interconnect structure to prevent oxidation of the metal interconnect and to prevent parasitic capacitance. The structure may further include one or more air gap structures formed upon the substrate and in between the graphene coated metal interconnect structures and capped with a dielectric layer.