Graphene Interconnects with Impurity-Doped Regions for Low Resistance

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Solution Overview

Problem

The miniaturization of interconnects in LSI structures leads to increased electric resistivity due to interfacial inelastic scattering of electrons and reliability degradation from stress migration or electromigration, which existing metallic materials like copper cannot effectively address.

Innovation Solution

A semiconductor device with a graphene layer containing impurities, featuring a first region of low resistance and a second region of higher resistance, where the second region has a side surface exposed to introduce impurities, preventing increased contact resistance by ensuring the first plug is in contact only with the low resistance region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interconnect size is miniaturized to increase integration density, then device scaling is improved, but electric resistivity increases due to interfacial inelastic scattering

Engineering Contradiction:

Improveintegration densityVSAvoidelectric resistivity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies parameter changes by introducing controlled impurity doping into the graphene layer to alter its electrical properties. By adjusting the impurity concentration in specific regions, the material's resistivity is modified to compensate for the increased scattering effects that occur at miniaturized dimensions. This allows the interconnect to maintain low resistance even when scaled down to smaller sizes for higher integration density.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents the increase in contact resistance between plugs and the graphene layer, maintaining low resistance and improving the reliability of interconnects in LSI structures.

Implementation Method 1

quantized conductance (what is called. Ballistic conductance) is generated in the graphene, and the graphene is expected to be an extremely low resistance material

Methodology Applied

Scientific EffectBallistic conductance: Conduction (electrical)

Implementation Method 2

introducing impurities into the graphene layer through the exposed side surface

Methodology Applied

Scientific EffectImpurity introduction: Absorption (physical)

Data Source

PatentUS9865547B2Semiconductor device and manufacturing method thereof

Publication Date: 2018.01.09 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a second region. The second region has a resistance higher than a resistance of the first region. The second region includes a side surface of an end of the graphene layer. The device further includes a first plug being in contact with the first region.