Graphene Protection Liner for Interconnect Via Isolation
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) are scaled down, the increased density and reduced spacing between conductive features lead to increased capacitance, power consumption, and time delay, making it challenging to maintain performance and manufacturing efficiency due to limitations in light diffraction and processing precision.
Innovation Solution
The use of a protection liner, such as graphene, on interconnect wires to prevent the formation of cavities that could disrupt air spacer structures and isolation, allowing for precise formation of interconnect vias without extending into the dielectric layer, thereby maintaining isolation and reducing electron scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If spacing between conductive features is reduced to increase density, then device density is improved, but capacitance and power consumption increase
Solution Approach 1:
Air spacer structures are introduced as intermediary elements between adjacent conductive features (interconnect wires). These air spacers, being non-conductive and having low dielectric constant, mediate the electromagnetic interaction between neighboring conductors, thereby reducing parasitic capacitance and power consumption while allowing higher device density
2Ease of manufacture
If interconnect via extends below topmost surface of interconnect wire, then via formation is simplified, but isolation and device performance deteriorate
Solution Approach 1:
A protection liner is deposited on the interconnect wire before via formation. This preliminary protective layer prevents the etching process from penetrating below the wire's topmost surface, thereby maintaining isolation and device performance while still allowing via formation to proceed. The protection liner acts as a pre-established barrier that guides the via formation process.
Solution Approach 2:
The protection liner serves as an intermediary layer between the interconnect wire and the etching process. It mediates the interaction by providing a controlled interface that allows via formation while preventing excessive etching that would compromise isolation and device performance
3Area of stationary object
If feature sizes are scaled down to reduce IC size, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The introduction of protection liners and air spacers changes the physical and chemical parameters of the interconnect structure. These additional layers provide better etch selectivity and process control, allowing for precise via formation even as feature sizes are scaled down. The protection liner's specific material properties enable controlled etching processes that maintain precision at smaller dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the processing window for forming interconnect vias, reduces capacitance, and enhances the reliability and efficiency of integrated chips by maintaining isolation and minimizing resistivity changes as feature sizes decrease.
Implementation Method 1
reduces electron scattering
Implementation Method 2
the resulting capacitance increases
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.