Ordered Graphene Nanoribbon Arrays for High-Density Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher density integrated circuits with smaller feature sizes and improved transistor performance, as graphene lacks a bandgap, making it unsuitable for digital devices unless fabricated as nanoribbons with widths less than 10 nm.
Innovation Solution
A semiconductor structure is formed using an ordered array of parallel graphene nanoribbons on a substrate, achieved by patterning a graphene layer, assembling nanowires as an etch mask, and etching to create parallel graphene nanoribbons, which can serve as a channel for semiconductor devices like field effect transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If graphene is used in transistor fabrication, then electron mobility and speed are improved, but the lack of bandgap causes poor Ion/Ioff ratios
Solution Approach 1:
The patent applies local quality by creating nanoribbon structures with specific width constraints (less than 10 nm, preferably less than 5 nm) to induce quantum confinement effects. This local dimensional control creates a bandgap in the graphene material itself, allowing the same graphene to exhibit both high electron mobility and appropriate switching characteristics for digital devices.
Solution Approach 2:
The patent changes the physical parameters of graphene by constraining its width to nanoscale dimensions through precise fabrication processes. This parameter change (width control) fundamentally alters the electronic properties of graphene, opening a bandgap while maintaining the high electron mobility that makes graphene attractive for high-speed transistors.
2Quantity of substance
If feature sizes are downscaled to achieve higher density, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action through the use of block copolymer self-assembly to pre-establish the nanoribbon pattern before graphene fabrication. The block copolymers spontaneously organize into ordered structures with controlled dimensions, providing a template that guides subsequent graphene nanoribbon formation. This preliminary patterning step achieves the required precision without demanding extreme manufacturing control in later steps.
Solution Approach 2:
The patent introduces block copolymers as an intermediary material that mediates the patterning process. These copolymers self-assemble into ordered structures that serve as a intermediary template, transferring the pattern to the graphene layer through controlled decomposition or etching. This intermediary approach simplifies the direct patterning of graphene at nanoscale dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density semiconductor structures with improved transistor performance by forming ordered arrays of parallel graphene nanoribbons, addressing the bandgap issue and enabling the fabrication of smaller, faster, and more efficient transistors.
Implementation Method 1
The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electrical field assisted assembly process
Data Source
AI summary
A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.