Graphene Seed Layer Circuit Board Structure for Etching Defect Prevention

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing manufacturing process for circuit boards often results in issues such as circuit undercut, peel-off, or shape deformation during the etching process, which affects signal transmission reliability and product quality due to the attack of etching solutions on the seed layer.

Innovation Solution

A circuit board structure and manufacturing method utilizing a graphene seed layer with alternating conductive and non-conductive regions, where the non-conductive regions provide insulation, eliminating the need for an additional etching process to remove the seed layer, and enhancing signal transmission and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an etching process is used to remove the seed layer, then the seed layer can be completely removed, but circuit undercut, peel-off, or shape deformation occurs due to etching solution attack

Engineering Contradiction:
Improvesignal transmission reliabilityVSAvoidcircuit shape precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The graphene seed layer is designed with spatially varying properties: conductive regions for signal transmission and non-conductive regions for insulation. This local differentiation allows the seed layer to serve multiple functions simultaneously - providing electrical connectivity where needed while preventing etching solution attack where required, thereby eliminating circuit undercut and peel-off issues without compromising signal transmission reliability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of completely removing the seed layer through etching (which causes harm), the patent converts the seed layer into a functional component by creating alternating conductive and non-conductive regions. The non-conductive regions act as protective barriers against etching solution attack, while the conductive regions maintain electrical connectivity. This transforms the previously harmful presence of the seed layer into a beneficial protective structure

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Manufacturing precision

If the seed layer is completely removed by etching, then no insulation issues remain, but the etching process causes circuit peel-off and deformation

Engineering Contradiction:
Improvecircuit shape precisionVSAvoidmanufacturing process simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The graphene seed layer is segmented into alternating conductive and non-conductive regions in a patterned arrangement. This segmentation allows different portions of the seed layer to perform different functions: conductive regions maintain electrical connectivity for signal transmission, while non-conductive regions provide insulation and protect against etching solution attack. This segmented approach resolves the contradiction by eliminating the need for complete seed layer removal while preventing circuit deformation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The graphene seed layer is designed to perform multiple functions simultaneously: it provides electrical connectivity through conductive regions, offers insulation through non-conductive regions, and serves as a protective barrier against etching solution attack. This multi-functionality eliminates the need for separate processes to achieve each function, simplifying the manufacturing process while improving circuit shape precision by preventing peel-off and deformation

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If an etching process is used to remove the seed layer, then the seed layer removal is achieved, but product yield decreases due to quality issues

Engineering Contradiction:
Improveproduct yieldVSAvoidproduct quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent converts the previously harmful presence of the seed layer (which caused yield loss through complete removal issues) into a beneficial protective structure. The non-conductive regions of the graphene seed layer serve as barriers that prevent etching solution attack on the circuit patterns, eliminating circuit undercut and peel-off defects. This transformation directly improves product quality and increases yield by eliminating the need for problematic complete seed layer removal

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the electrical conductivity parameter of the graphene seed layer in different regions, creating alternating conductive and non-conductive zones. This parameter change allows the seed layer to function as both an electrical conductor and an insulating protective barrier. By controlling the conductivity distribution, the patent prevents etching solution attack while maintaining necessary electrical connectivity, thereby improving product quality and yield without compromising reliability

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents common issues like circuit undercut and shape deformation, improving signal transmission reliability and product yield while also providing effective heat dissipation through the use of graphene's thermal conductivity.

Implementation Method 1

providing effective heat dissipation through the use of graphene's thermal conductivity

Methodology Applied
Scientific EffectThermal conductivity: Conduction (thermal)

Data Source

PatentUS11641713B2Circuit board structure and manufacturing method thereof
Publication Date: 2023.05.02 UNIMICRON TECH CORP
  • US11641713B2 patent drawing
  • US11641713B2 patent drawing
  • US11641713B2 patent drawing

AI summary

A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.