Graphene Adjustment Layers for Low-Resistance Semiconductor Interconnects
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in reducing resistance between layers to decrease power consumption.
Innovation Solution
The semiconductor device design incorporates graphene layers as adjustment layers to reduce resistance between the pad layer and the redistribution layer, with a specific structure including a substrate, passivation layers, redistribution layers, and barrier layers, and the use of graphene in the first and second adjustment layers to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional materials are used for adjustment layers, then manufacturing process is simpler, but resistance between layers is higher and power consumption increases
Solution Approach 1:
The patent uses graphene as a composite material for the adjustment layers between conductive layers. Graphene's unique two-dimensional structure and high electrical conductivity properties reduce resistance between layers, thereby reducing power consumption while maintaining structural integrity of the semiconductor device
Solution Approach 2:
The patent changes the material parameter of the adjustment layers from conventional materials to graphene. This parameter change exploits graphene's superior electrical conductivity to reduce inter-layer resistance and power consumption, while the thin-film nature of graphene maintains device compactness
2Productivity
If device dimensions are scaled down, then computing ability increases, but resistance between layers increases and quality/yield deteriorates
Solution Approach 1:
The patent applies graphene as a composite material in the adjustment layers to maintain low resistance even as device dimensions are scaled down. Graphene's high carrier mobility and conductivity compensate for the reduced scale effects, preserving signal integrity and device reliability at smaller dimensions
Solution Approach 2:
The patent applies graphene specifically at the critical interfaces between conductive layers where resistance is most problematic. This localized application of high-performance material targets the specific quality issues at layer interfaces without requiring complete redesign of the entire device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively decreases power consumption and improves the performance of semiconductor devices by reducing resistance, thereby addressing the challenges of scaling down semiconductor devices.
Implementation Method 1
The first adjustment layer and the second adjustment layer are formed of graphene... effectively decreases power consumption and improves the performance of semiconductor devices by reducing resistance
Data Source
AI summary
The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.