Graphene Stack Memory Cells Tunable Band Gap Scalability
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Solution Overview
Problem
Current non-volatile memory technologies face limitations in scalability and power requirements for inducing switching events in memory cells, particularly in interconnect layers and memory cell scalability.
Innovation Solution
The use of stacked graphene layers with a tunable band gap, where the conductivity is altered by applying an electrical field to define binary values in memory cells, allowing for reversible data storage with low power requirements and scalability to small process technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional non-volatile memory technologies (NAND flash, PCM, MRAM) are used, then data storage capability is achieved, but scalability to smaller process technologies is limited due to interconnect layer power delivery limitations and memory cell scalability constraints
Solution Approach 1:
The patent utilizes the tunable band gap parameter of graphene by controlling the stacking configuration (Bernal vs. rhombohedral) to achieve desired electrical conductivity states. This parameter change enables the memory cell to switch between conductive and insulating states with lower power requirements, resolving the contradiction between scalability and power consumption.
Solution Approach 2:
The invention employs a composite structure of multiple graphene layers with specific stacking arrangements (Bernal-stacked and rhombohedral-stacked configurations) to create a material system with tunable electrical properties. This composite approach enables both scalability and low-power operation by leveraging the unique properties of different graphene stacking configurations.
2Reliability
If conventional memory technologies are used, then data storage is achieved, but power consumption for sensing data and inducing switching events is high
Solution Approach 1:
The patent exploits the parameter change in band gap and electrical conductivity of graphene when transitioning between Bernal-stacked and rhombohedral-stacked configurations. This natural parameter change in the material properties enables reliable reversible data storage with minimal energy input, as the switching is driven by electrical field effects rather than high-power thermal or magnetic processes.
Solution Approach 2:
The invention replaces traditional high-power switching mechanisms (thermal, magnetic, or electrical breakdown) with an electrical field effect mechanism that utilizes the tunable band gap of graphene. This substitution dramatically reduces the power requirements for both sensing and switching operations while maintaining reliable reversible data storage.
3Power
If interconnect layers are designed to deliver sufficient power for switching events, then switching capability is achieved, but device complexity and power consumption increase
Solution Approach 1:
By changing the electrical field parameter applied to the graphene stack, the invention achieves switching between conductive and insulating states without requiring complex interconnect layers designed for high power delivery. The parameter change in graphene's electrical properties enables low-power switching, simplifying the interconnect architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the development of semiconductor memory devices capable of reversible data storage with low power consumption and scalability to ultra-small process technologies, leveraging the conductivity changes between Bernal-stacked and rhombohedral-stacked configurations of graphene layers.
Implementation Method 1
altering the in-plane conductivity of the graphene stack of each memory cell during programming of the memory cell
Implementation Method 2
leveraging the conductivity changes between Bernal-stacked and rhombohedral-stacked configurations of graphene layers
Data Source
AI summary
Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack. The in-plane conductivity of the graphene stack of each memory cell is altered during programming of the memory cell to define a binary value of bits stored in the memory cell.