Graphene Transistor Self-Aligned Gate Reduces Parasitic Resistance
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Solution Overview
Problem
The performance of graphene field effect transistors (FETs) is limited by parasitic series resistance in the access regions between source/drain contacts and the gated graphene channel, which increases as device dimensions shrink, and conventional doping methods like ion implantation damage the fragile graphene lattice.
Innovation Solution
A self-aligned gate structure is created using a bilayer metal gate stack with a second metal portion overhanging the first, allowing for directional deposition to form source and drain electrodes minimally spaced from the gate electrode, eliminating the need for lithographic alignment and ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to improve integration, then device density increases, but access resistance becomes comparable to channel resistance
Solution Approach 1:
By transitioning from a planar two-dimensional layout to a three-dimensional vertical structure, the patent enables source/drain electrodes to be positioned minimally spaced from the gate electrode edges without requiring lateral access regions. This vertical arrangement maintains low access resistance even as device dimensions are scaled down, allowing continued device density improvement without the access resistance penalty that would normally accompany scaling.
Solution Approach 2:
The conformal deposition process automatically positions the source/drain electrodes at the optimal location relative to the gate electrode. The deposition methodology inherently creates the minimal lateral spacing configuration, eliminating the need for separate alignment steps or access region design. This self-aligning feature ensures consistent low access resistance across scaled device dimensions.
2Object-affected harmful factors
If ion implantation is used to reduce access resistance, then electrical conductivity increases, but graphene lattice structure is damaged
Solution Approach 1:
The patent completely eliminates the ion implantation process from the fabrication methodology. Instead of attempting to dope the graphene, the invention achieves low access resistance through the geometric configuration of the electrodes themselves - specifically, by positioning the source/drain electrodes minimally spaced from the gate electrode edges through conformal deposition. This extraction of the harmful ion implantation step preserves the graphene lattice integrity while still achieving the desired electrical performance.
Solution Approach 2:
The patent replaces the mechanical ion implantation process with a chemical vapor deposition or atomic layer deposition process to form the electrodes. This substitution uses controlled chemical reactions to deposit conductive materials in a conformal manner, achieving the same electrical conductivity improvement without the mechanical damage caused by ion bombardment. The electrode geometry itself, rather than material doping, provides the resistance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic resistance and capacitance, enhancing device performance for high-frequency applications while preserving the graphene lattice integrity, enabling sublithographic spacing and compatibility with high-k dielectric materials.
Implementation Method 1
directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode
Data Source
AI summary
A method of forming a transistor structure is provided. The method includes forming a graphene layer on an insulating layer; forming a stack of a first metal portion and a second metal portion over the graphene layer, wherein sidewalls of the first metal portion are vertically coincident with sidewalls of the second metal portion; and laterally offsetting the sidewalls of the first metal portion relative to the sidewalls of the second metal portion by a lateral distance.