Graphene Transistors for Low-Temperature 3D Monolithic Integration
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Solution Overview
Problem
In three-dimensional monolithic integration, the high temperatures required for fabricating transistors in subsequent layers damage existing circuits, limiting the use of single crystal silicon and resulting in reduced performance due to the use of lower quality polysilicon for P-MOS transistors.
Innovation Solution
The integration of graphene transistors, which can be fabricated at lower temperatures without damaging back-end-of-line components and offer improved electron mobility, replacing traditional polysilicon transistors in subsequent layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature fabrication is used for subsequent layers, then transistor performance is improved, but existing circuits are damaged
Solution Approach 1:
The patent changes the fabrication temperature parameter from high temperature (conventional silicon process) to low temperature (graphene process), enabling subsequent layer fabrication without damaging existing circuits while maintaining transistor performance
Solution Approach 2:
The patent uses graphene as a composite material replacement for traditional silicon-based transistors in subsequent layers, combining the benefits of low-temperature fabrication with high electron mobility to resolve the contradiction between performance and thermal damage
2Reliability
If single crystal silicon is used for subsequent layers, then transistor performance is improved, but fabrication temperature becomes too high
Solution Approach 1:
The patent changes the material parameter from single crystal silicon to graphene, which enables low-temperature fabrication while maintaining or improving electron mobility and transistor performance
Solution Approach 2:
The patent employs a disposable sacrificial layer (such as silicon dioxide or organic material) that is temporarily used during fabrication and then removed, enabling low-temperature graphene transistor formation without requiring high-temperature crystallization processes
3Temperature
If polysilicon is used for P-MOS transistors, then fabrication temperature is reduced, but electron mobility decreases
Solution Approach 1:
The patent uses graphene as a superior material that combines low-temperature fabrication capabilities with high electron mobility, eliminating the trade-off present in polysilicon-based approaches
Solution Approach 2:
The patent changes the material composition from polysilicon to graphene, fundamentally altering the electron transport properties while maintaining low fabrication temperature requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Graphene transistors provide optimized performance with enhanced electron mobility while avoiding thermal damage to existing circuits, enabling improved three-dimensional monolithic integration with better transistor performance and alignment accuracy.
Implementation Method 1
The graphene layer 514 is grown on a conductive layer 512 (e.g., nickel or copper) of the transitional substrate 510
Implementation Method 2
offer improved electron mobility
Data Source
AI summary
A semiconductor device and methods of making a semiconductor device using graphene are described. A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.