Graphene Wire Doping for Semiconductor Interconnects
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Solution Overview
Problem
The use of bromine (Br) as an additive element in multi-layered graphene structures for reducing resistance in semiconductor devices can lead to corrosion and etching of metal materials like W or Ti, particularly at contact points with the upper-layer graphene wires.
Innovation Solution
A semiconductor device design that differentiates between doping regions for multi-layered graphene wires in memory cell and peripheral circuit regions, where Br is added to the memory cell region for reduced resistance but not in the peripheral circuit region to prevent corrosion with contact metals, using a catalytic metal layer and surface protection layers to manage graphene growth and prevent metal interaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bromine (Br) is added as an additive element in multi-layered graphene structures to reduce resistance, then the resistance of graphene wires is reduced, but metal materials like W or Ti are etched and corroded at contact points
Solution Approach 1:
The patent applies different treatments to different regions of the graphene wire structure. Specifically, bromine doping is applied only to the lower-layer graphene wire in the memory cell region, while the upper-layer graphene wire in the peripheral circuit region remains undoped. This local differentiation allows resistance reduction where needed while preventing corrosion at metal contact points.
Solution Approach 2:
The graphene wire structure is segmented into multiple layers (lower-layer and upper-layer graphene wires) and multiple regions (memory cell region and peripheral circuit region). This segmentation enables selective application of bromine doping to specific segments, resolving the contradiction between needing low resistance and avoiding metal corrosion.
2Reliability
If multi-layered graphene structure is used to reduce wire resistance, then electrical conduction is improved, but complexity of device structure increases
Solution Approach 1:
The patent introduces catalytic metal layers and surface protection layers at specific locations within the graphene wire structure. These layers are placed locally where needed - catalytic metal layers beneath the graphene for controlled growth, and surface protection layers where metal contacts are formed - rather than uniformly throughout the entire structure, thus managing complexity while achieving the desired electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the resistance of graphene wires in memory cell regions while preventing etching and corrosion in peripheral circuit regions, enhancing overall element characteristics and maintaining low wire resistance without compromising metal integrity.
Implementation Method 1
a first graphene wire (20a) formed above the substrate and including a multi-layered graphene layer (23a) having a preset impurity doped therein
Implementation Method 2
the mobility of carriers (electrons or holes) in a graphene sheet is raised by adding an element such as Br in between graphene layers and thus the resistance thereof can be reduced
Implementation Method 3
using a catalytic metal layer and surface protection layers to manage graphene growth
Data Source
AI summary
According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.