Graphene Wire Interconnects for Sub-40nm Low Resistance
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Solution Overview
Problem
As metal wires in leading-edge devices miniaturize, their electrical resistivity increases due to electronic interface inelastic scattering, leading to significant signal delay in LSI performance, necessitating a material alternative to suppress wire resistance.
Innovation Solution
The use of graphene wires, formed on a substrate with a metal film and metal part of different metals or alloys, where the metal film facilitates single-layer graphene growth and the metal part facilitates multilayer graphene growth, reducing wire resistance by controlling the facet angle and carbon solid solubility for large-area graphene formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal wire dimensions are miniaturized to reduce device size, then device integration density is improved, but electrical resistivity increases due to electronic interface inelastic scattering
Solution Approach 1:
The invention changes the material parameter from conventional metal to graphene, which has fundamentally different electrical conduction properties. Graphene's two-dimensional structure and high carrier mobility allow it to maintain low electrical resistivity even at sub-40nm dimensions where conventional metals suffer from increased scattering effects
Solution Approach 2:
The invention uses a composite structure consisting of graphene wires formed on metal substrates (such as copper or nickel). The metal substrate provides mechanical support and facilitates graphene growth, while the graphene layer provides low-resistance conduction path, combining the advantages of both materials
2Length of moving object
If wire width and height are reduced below mean free path of conduction electron, then device miniaturization is achieved, but electrical resistivity increases significantly
Solution Approach 1:
The invention changes the fundamental conduction mechanism by using graphene, where charge carriers (electrons and holes) exhibit high mobility due to linear dispersion relation near Dirac points. This allows effective conduction even when wire dimensions are below the mean free path of conduction electrons in conventional metals
3Length of moving object
If wire length is increased to extend signal transmission, then device functionality is improved, but RC delay increases due to higher wire resistance
Solution Approach 1:
The invention changes the resistivity parameter by using graphene, which has inherently lower electrical resistivity compared to conventional metals like copper. This reduction in resistivity directly decreases the RC delay in long wire interconnects, enabling faster signal transmission across the chip
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a low-resistant wire suitable for minute wire applications below 40 nm, effectively reducing RC delay and improving reliability by decreasing electrical resistivity.
Implementation Method 1
a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part
Implementation Method 2
the metal film and the metal part are formed using different metals or alloys from each other
Implementation Method 3
the graphene wire is electrically connected to the metal film; decreasing electrical resistivity
Implementation Method 4
the metal film and the metal part are formed using different metals or alloys from each other; facilitating multilayer graphene growth
Data Source
AI summary
A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.