Graphene Wiring via Oriented Catalyst Layers for Low Resistivity
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Solution Overview
Problem
The miniaturization of LSI wiring structures leads to increased electric resistivity due to interfacial inelastic scattering of electrons and reliability degradation from stress migration or electromigration, despite the use of low-resistance materials like copper, and polycrystalline graphene with small grain diameters suffers from high resistance due to crystal defects.
Innovation Solution
A method for manufacturing semiconductor devices involving the formation of a co-catalyst layer and a catalyst layer with specific crystal structures on a semiconductor substrate, where the (111) plane of the face-centered cubic structure or the (002) plane of the hexagonal close-packed structure is oriented parallel to the substrate surface, facilitating the growth of a high-quality graphene layer with reduced crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If copper is used as LSI wiring material to achieve low resistance, then electrical conductivity is improved, but reliability degrades due to stress migration or electromigration
Solution Approach 1:
The invention changes the material parameter from conventional metals (copper, aluminum) to graphene, which has fundamentally different electrical and mechanical properties. Graphene's two-dimensional structure and high carrier mobility provide low resistance while its mechanical strength and thermal conductivity improve reliability by reducing stress migration and electromigration effects
Solution Approach 2:
The invention uses composite structures including graphene layers combined with catalyst layers (such as nickel, cobalt, or iron) and co-catalyst layers (such as tungsten, molybdenum, or titanium). This composite approach enables controlled graphene growth while maintaining the underlying substrate's mechanical support, achieving both low resistance and high reliability
2Productivity
If wiring structure is miniaturized to increase integration density, then device capacity is improved, but electric resistivity increases due to interfacial inelastic scattering of electrons
Solution Approach 1:
The invention changes the dimensional parameter of the wiring material from three-dimensional bulk metals to two-dimensional graphene. This dimensional reduction eliminates grain boundaries and reduces interfacial scattering, maintaining low resistivity even as wiring dimensions are miniaturized for higher integration density
Solution Approach 2:
The invention replaces conventional metal-based electrical conduction mechanisms with graphene's unique ballistic transport mechanism. Electrons in graphene can travel long distances without scattering, substituting the diffusive transport in metals with ballistic transport, thereby maintaining low resistance at miniaturized dimensions
3Adaptability or versatility
If polycrystalline graphene with small grain diameter is used, then material flexibility is improved, but wiring resistance increases due to electron scattering at crystal defects
Solution Approach 1:
The invention performs preliminary actions by carefully controlling the growth conditions of graphene on catalyst layers before the graphene is used for wiring. By optimizing parameters such as temperature, pressure, and catalyst composition during the growth stage, the invention produces graphene with large domain sizes and minimal crystal defects, thereby achieving low resistance while maintaining the flexibility needed for wiring applications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a graphene layer with low resistance and excellent heat-resistant properties, suitable for LSI wiring, by minimizing electron scattering and enabling the formation of high-quality graphene with enlarged domains, even as device elements further miniaturize.
Implementation Method 1
forming a catalyst layer on the co-catalyst layer, wherein the catalyst layer has a face-centered cubic structure or a hexagonal close-packed structure
Data Source
AI summary
According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.