Graphene Wiring Structure Etching for Low-Damage Contact Formation
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Solution Overview
Problem
As semiconductor devices shrink, the electrical characteristics of silicon channels reach limits, necessitating the development of channels with higher charge mobility, such as 2-dimensional materials, and the integration of graphene electrodes, which requires advanced manufacturing methods for effective use.
Innovation Solution
A method involving alternately stacking graphene electrode layers and hexagonal boron nitride insulation layers, using fluorine-based dry etching and reactive ion etching processes to form openings and contact plugs, ensuring precise exposure and minimization of damage to the layers, thereby enabling the formation of efficient wiring structures and semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching processes are used on graphene electrode layers, then etching can be performed, but the graphene layers suffer significant damage and integrity is compromised
Solution Approach 1:
The patent introduces an intermediary material layer between the graphene electrode layer and the etching process. This intermediary layer acts as a protective mediator that allows etching to proceed while preventing direct damage to the graphene, thus resolving the contradiction between etchability and graphene integrity
Solution Approach 2:
The patent employs self-aligned etching processes where the graphene structure itself or previously formed layers serve as the etch mask. This self-service approach eliminates the need for separate mask layers, enabling precise etching while preserving graphene integrity through controlled exposure
2Productivity
If the size of semiconductor devices is reduced to improve integration density, then device scaling is achieved, but the electrical characteristics of silicon channels reach performance limits
Solution Approach 1:
The patent changes the material parameter of the channel from conventional silicon to graphene, which fundamentally alters the electrical characteristics. Graphene's superior charge mobility and electrical conductivity enable continued performance improvement as device size scales down, resolving the contradiction between integration density and electrical performance
Solution Approach 2:
The patent creates a composite structure combining graphene electrode layers with insulating layers in a vertically stacked configuration. This composite material approach enables both high integration density through vertical stacking and superior electrical performance through graphene's inherent properties
3Adaptability or versatility
If multiple graphene electrode layers are stacked to form complex wiring structures, then device functionality is improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent segments the wiring structure into multiple discrete graphene electrode layers separated by insulating layers. Each layer can be independently patterned and etched using standardized processes, which maintains manufacturing simplicity while achieving complex overall functionality through the stacked configuration
Solution Approach 2:
The patent transitions from planar 2D wiring structures to 3D vertically stacked structures. By adding the vertical dimension, the patent achieves enhanced device functionality and higher integration density without proportionally increasing lateral manufacturing complexity, as each layer can be processed using similar fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the creation of semiconductor devices with improved electrical characteristics by maintaining the integrity of graphene electrodes and insulation layers, facilitating effective charge mobility and reducing damage during the etching process.
Implementation Method 1
etching a first insulation layer through a first dry etching process using an etching gas including fluorine (F) to form an opening exposing an upper surface of a first electrode layer
Implementation Method 2
removing a portion of the first electrode layer exposed by the opening through a reactive ion etching (RIE) process using oxygen plasma and/or hydrogen plasma to enlarge the opening
Data Source
AI summary
In a method, an electrode layer and an insulation layer are alternately and repeatedly stacked on a substrate. A first insulation layer is etched through a first dry etching process using an etching gas including fluorine to form an opening exposing a first electrode layer. The first electrode layer exposed by the opening is partially removed through an RIE process using oxygen and/or hydrogen plasma to enlarge the opening so that a second insulation layer is exposed. The second insulation layer exposed by the opening is etched through a second dry etching process using an etching gas including fluorine to enlarge the opening so that a second electrode layer is exposed. A contact plug is formed in the enlarged opening.