Graphene Wiring Doping for Low Resistance
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Solution Overview
Problem
In miniaturized multi-layered LSI and 3D memory, metal wiring faces increased delay due to high resistance and capacitance, with copper wiring suffering from reliability issues like stress-migration and electromigration, and graphene wiring becomes semiconductive at thin widths, leading to increased resistance.
Innovation Solution
A graphene wiring structure is developed with a catalyst layer, a graphene layer, and dopant layers on the sides, where atomic or molecular species are intercalated or disposed to enhance conductivity, reducing scattering effects and maintaining low resistance even at narrow widths by adjusting the graphene layer width and using specific dopants like N2, B, O2, or metals to modify the band structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the graphene wiring is made thin to reduce wiring delay, then the wiring resistance increases due to quantum confinement effect and scattering effect, but reducing wiring thickness is necessary to maintain low resistance and high current density tolerance
Solution Approach 1:
The patent applies parameter changes by introducing dopant concentrations and types as controllable parameters. By adjusting the dopant concentration and selecting specific dopant types, the electrical properties of graphene can be tuned to maintain low resistance even at thin wiring dimensions, thus resolving the contradiction between reliability and manufacturing precision
Solution Approach 2:
The patent creates a composite structure by combining graphene with dopant materials. This composite approach allows the graphene-dopant system to exhibit enhanced electrical conductivity compared to pure graphene, enabling thin wirings to maintain low resistance while preserving high current density tolerance
2Manufacturing precision
If copper wiring is used to decrease wiring resistance, then the wiring resistance decreases, but reliability deteriorates due to stress-migration and electromigration
Solution Approach 1:
The patent positions graphene as a replacement material that, while potentially more complex to manufacture, offers superior long-term reliability and durability. The graphene wiring structure is designed to be more robust against degradation mechanisms, effectively trading manufacturing complexity for extended service life and maintained performance
Solution Approach 2:
By creating a graphene-based composite wiring structure with dopant integration, the patent achieves a material system that combines low resistance with high reliability. The composite structure provides both the electrical performance needed to replace copper and the mechanical/chemical stability required to avoid stress-migration and electromigration issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The graphene wiring achieves lower volume resistivity and higher current density tolerance, maintaining low resistance and reliability, with the dopant layers effectively preventing the graphene from turning semiconductive, even at widths as small as 10 nm, resulting in a significant reduction in resistance compared to undoped graphene.
Implementation Method 1
a dopant layer on side surfaces of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer
Implementation Method 2
Application of a carbon-based material such as a carbon nanotube and a graphene with an excellent physical property such as high current density tolerance, electric conduction property
Implementation Method 3
growing graphene on a catalyst layer that has been formed in a wiring pattern
Data Source
AI summary
A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer.