Graphene Wiring via Segmented Thermal Processing
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Solution Overview
Problem
The high formation temperature of graphene films using CVD methods, typically above 450°C, is incompatible with certain device structures like magnetic transformation type memory elements, causing phase changes or collapse, and results in increased electron scattering and wiring resistance due to higher defect densities at lower temperatures.
Innovation Solution
A semiconductor device structure where graphene wiring is applied using a low-temperature process for semiconductor elements and a separate high-temperature process for forming graphene wires, with substrates stacked at the wafer level, ensuring minimal thermal influence on the element structure and achieving low resistance graphene wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If graphene films are formed using CVD method at high temperature (above 450°C), then low resistance graphene wires are achieved, but device structures like magnetic transformation type memory elements suffer phase changes or collapse
Solution Approach 1:
The patent divides the formation process into two separate stages: first forming the device structure at low temperature, then forming the graphene wiring layer at high temperature in a subsequent process. This segmentation allows each component to be optimized for its specific temperature requirements without compromising the other.
Solution Approach 2:
The device structure is formed in advance at low temperature before the graphene wiring is deposited. This preliminary action ensures that temperature-sensitive components are already in place and protected, allowing the high-temperature graphene formation to proceed without damaging the underlying structure.
2Stability of the object's composition
If graphene films are formed at lower temperature, then device structure integrity is maintained, but electron scattering increases and wiring resistance rises
Solution Approach 1:
The formation process is segmented into distinct temperature stages: low-temperature device formation followed by high-temperature graphene wiring formation. This resolves the contradiction by allowing the device structure to experience only low temperatures while the graphene wires achieve low resistance through high-temperature processing.
Solution Approach 2:
The patent changes the temperature parameter at different stages of the formation process. The device structure is formed at low temperature to maintain integrity, then the temperature is increased for graphene deposition to achieve low resistance, effectively using parameter change to resolve the contradiction.
3Ease of operation
If single-layer graphene is used, then transparency and flexibility are improved, but mechanical strength and electrical conductivity decrease
Solution Approach 1:
The patent employs multi-layer graphene structures where multiple graphene layers are stacked to create a composite material. This composite approach maintains the inherent flexibility and transparency of graphene while enhancing electrical conductivity and mechanical strength through the synergistic effect of multiple layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the application of low-resistance graphene wiring to low-temperature coping device elements, enhancing element characteristics by reducing electron scattering and maintaining the integrity of the device structure.
Implementation Method 1
graphene has a quantization-conduction characteristic (ballistic conduction characteristic) like a carbon nano-tube and conducts electricity by quantization
Implementation Method 2
the graphene structure itself is an extremely thin film and can be formed by use of a CVD method
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires.