Graphic Memory Controller Parallel Write Bandwidth
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Solution Overview
Problem
Conventional methods for writing data to graphic memories in LCD drivers are limited in speed, failing to meet the demand for high-quality moving pictures due to the minimum write cycle time of graphic memory, which restricts data writing speed beyond a certain threshold, especially in higher resolution devices like WQVGA, HVGA, or VGA.
Innovation Solution
The method involves separating the graphic memory into multiple areas and using a controller to latch and write data simultaneously to these areas using different clock signals, allowing for non-consecutive writing in time and space, thereby increasing the write bandwidth and speed by distributing the data input across multiple memory areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is sequentially written to the same graphic memory area, then the writing operation is simple, but the data writing speed is limited by the minimum write cycle time
Solution Approach 1:
The graphic memory is divided into multiple separate memory areas (first memory area and second memory area). Data is distributed and written to these different areas simultaneously or alternately, allowing parallel write operations that bypass the sequential write cycle time limitation of a single memory area, thereby increasing overall data writing speed
Solution Approach 2:
The patent transitions from single-dimension sequential writing to multi-dimension parallel writing by utilizing multiple memory areas. The controller manages data distribution across these areas using different clock signals, effectively adding a spatial dimension to the write operation that enables simultaneous writes and increases bandwidth
2Speed
If the clock signal frequency is increased to improve data writing speed, then the writing speed increases, but the system requires high-speed clock signals that may not be available or practical
Solution Approach 1:
By segmenting the write operation across multiple memory areas with different clock signals, the system can process data at lower individual clock frequencies while achieving higher overall throughput through parallel operations, reducing the need for high-frequency clock signals and associated energy consumption
3Productivity
If data is written sequentially to meet the minimum write cycle time, then the write operation is reliable, but the bandwidth and access time are limited
Solution Approach 1:
Dividing the graphic memory into multiple areas enables parallel write operations, increasing the effective write bandwidth by allowing multiple data streams to be written simultaneously to different memory areas, thereby reducing total access time and improving productivity
Solution Approach 2:
The system maintains continuous data flow to the graphic memory by utilizing multiple memory areas and clock signals, ensuring that the write operation continues without interruption or idle cycles, thereby maximizing bandwidth utilization and reducing access time
Data Source
AI summary
A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space.