Graphical Programming for Heterogeneous Hardware Deployment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional text-based programming environments require advanced technical skills, limiting non-expert users in efficiently utilizing computer systems for modeling and controlling complex physical systems, such as instrumentation and industrial automation, due to the abstraction gap between conceptual modeling and implementation.
Innovation Solution
A computer-implemented system that automatically generates hardware-level functionality for parallel system-on-chip implementations, including floating-point math functionality, on heterogeneous hardware components like FPGAs, DSP cores, and GPUs, based on graphical or textual programs, allowing users to define instrument functionality without explicit partitioning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional text-based programming environments are used, then programming functionality is achieved, but user accessibility is limited due to requiring advanced technical skills
Solution Approach 1:
The patent replaces text-based programming mechanics with graphical programming mechanics. Users interact with visual blocks and diagrams instead of text code, substituting the mechanical action of typing and parsing text with dragging, dropping, and connecting graphical elements. This reduces the technical skill barrier while maintaining programming functionality.
Solution Approach 2:
The patent introduces a graphical programming environment as an intermediary layer between the user and the underlying hardware/system. This intermediary automatically handles the translation from graphical representations to executable code or configuration, shielding users from complex programming details while enabling sophisticated system control.
2Ease of operation
If high-level programming languages are used, then abstraction from hardware is achieved, but direct hardware control efficiency is reduced
Solution Approach 1:
The patent segments the programming task into graphical high-level logic definition and automatic low-level code generation. The graphical environment handles abstract logic design easily, while an underlying compiler or interpreter automatically translates to efficient hardware-specific code, separating the ease of high-level programming from the efficiency of low-level execution.
Solution Approach 2:
The system performs preliminary actions by automatically generating and optimizing low-level code during the compilation or interpretation phase. This preliminary translation ensures that while users work at a high abstract level, the generated code is already optimized for hardware efficiency, eliminating the need for users to manually optimize for both ease and efficiency.
3Manufacturing precision
If manual hardware configuration is performed, then precise hardware control is achieved, but development time and complexity increase
Solution Approach 1:
The patent enables self-service by allowing the system to automatically generate hardware configuration code from graphical program definitions. The programming environment itself performs the tedious task of translating high-level graphical logic into precise hardware control instructions, eliminating manual configuration work while maintaining precision.
Solution Approach 2:
The system performs preliminary hardware configuration generation during the programming phase. By automatically producing optimized hardware control code before deployment, the system eliminates time-consuming manual configuration steps while ensuring precise hardware control through systematic code generation and optimization.
Data Source
AI summary
System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.