Graphical Program Hardware Synthesis via Descriptive Directives
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Graphical programming tools face challenges in efficiently specifying and managing hardware implementations for programmable hardware elements, leading to complex, error-prone processes and the need for multiple divergent versions to meet varying performance and resource utilization requirements.
Innovation Solution
A system and method for specifying and managing hardware implementations of graphical programs by storing descriptive directives associated with the program, which can be used by synthesis tools to generate hardware configuration programs for deployment to programmable hardware elements, allowing users to select optimization levels and configure memory resources interactively through a graphical user interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the graphical program is redesigned to achieve fast throughput (1 cycle/sample), then performance is improved, but hardware resource utilization increases
Solution Approach 1:
The patent implements dynamic configuration of hardware resources through a runtime system that can adjust the degree of parallelism and resource allocation based on performance requirements. The system allows dynamic selection between different implementation versions (e.g., unrolled vs. non-unrolled loops) without requiring manual redesign, enabling the hardware to adapt its resource utilization to meet throughput targets.
Solution Approach 2:
The invention changes key hardware implementation parameters such as initiation interval, unroll factor, and pipeline depth through software-controlled synthesis directives. By modifying these parameters, the system can achieve different throughput levels (e.g., 1 cycle/sample) without fundamentally redesigning the graphical program, thus managing the trade-off between performance and resource utilization through parameter adjustment rather than structural redesign.
2Speed
If more registers are inserted to execute at 160 MHz, then performance is improved, but hardware resource utilization increases
Solution Approach 1:
The system dynamically determines the appropriate initiation interval and pipeline configuration to achieve target execution frequencies like 160 MHz. Rather than statically inserting registers, the runtime synthesis process automatically inserts the necessary registers and pipeline stages based on the desired clock frequency and performance targets, optimizing resource usage for the specific frequency requirement.
Solution Approach 2:
The patent performs preliminary analysis of the graphical program to identify critical paths and register insertion points before synthesis. This preliminary action allows the system to pre-calculate the optimal register placement and pipeline depth required to achieve 160 MHz operation, minimizing resource utilization while meeting the frequency target.
3Adaptability or versatility
If multiple versions of the graphical program are maintained for different requirements, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal graphical program that can generate multiple hardware implementation versions through a single source. The runtime synthesis system acts as a multi-functional engine that can produce different hardware configurations (different initiation intervals, unroll factors, pipeline depths) from the same graphical program, eliminating the need to maintain multiple divergent versions while preserving full adaptability to different performance and resource requirements.
4Manufacturing precision
If the designer manually specifies hardware implementation details, then manufacturing precision is improved, but ease of manufacture worsens
Solution Approach 1:
The system enables self-service hardware synthesis by automatically analyzing the graphical program and generating optimized hardware implementations without requiring manual specification of implementation details. The runtime synthesis engine autonomously determines optimal initiation intervals, unroll factors, and resource allocation based on performance targets, providing manufacturing precision while eliminating the tedious manual specification process for algorithm designers.
Solution Approach 2:
The patent introduces a runtime synthesis system as an intermediary between the high-level graphical program and the hardware implementation. This intermediary automatically translates graphical program semantics into hardware synthesis directives, preserving implementation precision while shielding the designer from complex hardware specification tasks. The intermediary handles the complexity of hardware optimization algorithms and resource allocation automatically.
Data Source
AI summary
System and method for managing and specifying hardware implementation of a graphical program. A graphical program that implements an algorithm is stored in a memory of a computer system. The graphical program meets one or more first specified implementation requirements and is targeted for deployment to a programmable hardware element. A plurality of sets of descriptive directives are also stored in the memory, where the descriptive directives are associated with the graphical program and specify one or more additional specified implementation requirements, e.g., memory resource implementations, optimization directives, and so forth, where the additional directives result from programmatic and/or user-specification. Each set of descriptive directives is useable by a synthesis tool to generate a respective hardware configuration program for deployment to the graphical programmable hardware element.