Graphics Accelerator Video Decoding via Pipeline Reconfiguration
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Solution Overview
Problem
Current devices supporting 3D-graphics applications and compressed digital film reproduction face challenges in reducing hardware costs and enhancing graphics card functions, as they require separate video decoders and graphics processors, leading to inefficiencies in resource utilization.
Innovation Solution
The method involves using a graphics accelerator to decode video streams by modifying and extending existing APIs, allowing the graphics pipeline to emulate video decoding processes, thereby reusing computation power and algorithms originally intended for graphics rendering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate video decoders and graphics processors are used, then video decoding function is achieved, but hardware cost increases and device complexity increases
Solution Approach 1:
The graphics processor is designed to perform both traditional graphics rendering functions and video decoding functions by utilizing its existing parallel processing architecture. The vertex processing units and fragment processing units are configured to execute video decoding algorithms, allowing a single device to serve multiple purposes and eliminate the need for separate dedicated video decoder hardware.
2Reliability
If separate video decoders and graphics processors are used, then video decoding function is achieved, but hardware cost increases
Solution Approach 1:
The graphics processor is designed to perform both traditional graphics rendering functions and video decoding functions by utilizing its existing parallel processing architecture. The vertex processing units and fragment processing units are configured to execute video decoding algorithms, allowing a single device to serve multiple purposes and eliminate the need for separate dedicated video decoder hardware.
3Device complexity
If graphics accelerator is used for video decoding, then hardware cost is reduced and device complexity is reduced, but computation algorithm compatibility must be extended
Solution Approach 1:
The graphics processor dynamically reconfigures its processing units between graphics rendering mode and video decoding mode. The same hardware resources (vertex processors, fragment processors, memory units) are flexibly allocated based on the current operational requirement, enabling the system to adapt to different computational tasks without requiring dedicated hardware for each function.
Data Source
AI summary
A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context.