Graphics System Compression for Display Buffer Blit
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Solution Overview
Problem
The increasing resolution of displays and cost pressures to reduce PCIe bus bandwidth threaten the ability of multi-graphics processing systems with Integrated Graphics Processors (IGPs) and discrete Graphics Processing Units (dGPUs) to maintain acceptable frame rates, especially in low-cost devices, as the bandwidth may become insufficient for blit operations.
Innovation Solution
Implementing compression techniques using video encoders and decoders to transfer compressed frames between the dGPU and IGP over a limited intra-system bus, allowing for high-resolution display support and power-efficient operation, leveraging industry-standard compression algorithms like H.264, H.265, VP8, and VP9 to reduce data size by up to ten-fold, and utilizing a PCIe interface with fewer lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If display resolution is increased, then image quality is improved, but bandwidth requirement increases
Solution Approach 1:
The patent applies compression techniques that change the parameter of data representation by encoding video frames in a compressed format (e.g., H.264, H.265, VP8, VP9) rather than uncompressed format. This parameter change reduces the bandwidth requirement for transferring frame data from dGPU to IGP while maintaining the high display resolution, achieving up to ten-fold reduction in data size.
2Ease of manufacture
If PCIe bus bandwidth is reduced, then hardware cost is reduced, but frame rate performance deteriorates
Solution Approach 1:
The patent changes the parameter of data transmission by implementing compression techniques on the dGPU before transferring frames to the IGP. This allows the system to use lower bandwidth PCIe interfaces (e.g., 4-lane or 2-lane configurations) while maintaining acceptable frame rates, as the compressed data requires less bandwidth for transmission.
Solution Approach 2:
The patent introduces compression and decompression operations as intermediary processes in the data transmission path between dGPU and IGP. The dGPU compresses frames before transmission, and the IGP decompresses them after reception, acting as mediators that enable efficient data transfer over limited bandwidth interfaces.
3Productivity
If dGPU is used for rendering, then graphics performance is improved, but power consumption increases
Solution Approach 1:
The patent changes the parameter of data transmission efficiency through compression, which reduces the time and energy required for the blit operation (transferring rendered frames from dGPU to IGP). By compressing frames on the dGPU before transfer and decompressing on the IGP, the system reduces the duration of high-power operations and enables the use of lower-power, lower-bandwidth PCIe interfaces.
Data Source
AI summary
A graphics system includes an integrated graphics processor and a discrete graphics processing unit. An intra-system bus coupled data from the discrete graphics processing unit to the integrated graphics processor. In a high performance mode the discrete graphics processing unit is used to render frames. Compression techniques are used to aid in the data transfer over an intra-system bus interface.