Graphics Compute Tile Interleave for Memory Traffic Reduction
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Solution Overview
Problem
Current graphics processing systems face high memory traffic and inefficiencies due to the need to frequently access external memory for intermediate image data during the rendering of graphical images, as they write and read render targets, leading to unnecessary data processing and memory bandwidth consumption.
Innovation Solution
The system interleaves graphics rendering operations and compute shader operations, maintaining intermediate results on-chip using a tile buffer and optimizing data access patterns to reduce external memory access by converting compute shaders to operate with a tiled access pattern and removing unnecessary memory barriers, allowing data to be processed and stored within the on-chip cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If intermediate image data is written to external memory and read back for subsequent rendering operations, then the graphics processing can proceed with multiple render targets, but external memory traffic increases significantly and power efficiency deteriorates
Solution Approach 1:
The patent segments the rendering process into tile-level operations, where intermediate image data is divided into smaller tile segments that can be processed and retained in on-chip memory. This segmentation allows different render targets to operate on different tiles simultaneously, enabling multi-render target capability while keeping data in fast on-chip memory rather than external memory, thus reducing power consumption.
Solution Approach 2:
The patent introduces a new dimension of parallelism by allowing multiple render targets to operate concurrently on different tile segments within the same rendering pass. This dimensional expansion from sequential multi-RT operations to parallel tile-level operations enables versatile multi-render target processing while maintaining data in on-chip memory, avoiding external memory access and improving power efficiency.
2Adaptability or versatility
If intermediate image data is frequently accessed from external memory during rendering, then rendering flexibility is maintained, but rendering performance and productivity decrease due to memory bandwidth constraints
Solution Approach 1:
The patent performs preliminary actions by pre-fetching and storing tile segments into on-chip memory before they are needed for subsequent render target operations. This preliminary data preparation eliminates the need for frequent external memory access during the actual rendering process, maintaining rendering flexibility while significantly improving performance by keeping data in fast on-chip memory.
Solution Approach 2:
The patent introduces on-chip memory as an intermediary between the rendering units and external memory. This intermediary layer allows rendering operations to access tile data quickly from on-chip memory without directly accessing external memory, thereby maintaining rendering flexibility while improving productivity by avoiding external memory bandwidth constraints.
3Adaptability or versatility
If compute shaders are used for post-processing operations on intermediate images, then processing capability is enhanced, but external memory access requirements increase and power consumption rises
Solution Approach 1:
The patent merges the compute shader operations with the graphics rendering operations by allowing both to access and process tile data from the same on-chip memory. This merging eliminates the need for separate external memory access for compute shader operations, enhancing processing capability while reducing power consumption by keeping all data processing within the on-chip memory domain.
4Reliability
If render targets are written to and read from external memory in sequence, then correct data dependency ordering is maintained, but memory bandwidth is consumed and processing time increases
Solution Approach 1:
The patent applies local quality control by implementing fine-grained data dependency management at the tile level rather than requiring global memory access ordering. This allows different tile segments to be processed in parallel with their own local data dependencies satisfied from on-chip memory, maintaining data dependency correctness while reducing processing time by eliminating sequential external memory access.
Data Source
AI summary
A graphics system interleaves a combination of graphics renderer operations and compute shader operations. A set of API calls is analyzed to determine dependencies and identify candidates for interleaving. A compute shader is adapted to have a tiled access pattern. The interleaving is scheduled to reduce a requirement to access an external memory to perform reads and writes of intermediate data.