Contiguous Address Allocation for Graphics Data Storage

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Solution Overview

Problem

Current data storage methods for graphics processing units (GPUs) are inefficient in managing and retrieving different data types, leading to potential errors and increased processing time due to the need to track individual storage device addresses and lack of contiguous address allocation.

Innovation Solution

Implementing a method where a processing unit assigns contiguous ranges of addresses for different data types within a storage device or IOMMU, allowing for efficient storage and retrieval by tracking address ranges rather than individual addresses, and utilizing a common memory cache to store and invalidate data types quickly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If individual storage device addresses are tracked for different data types, then data storage flexibility is maintained, but processing time increases and errors occur due to the complexity of managing individual addresses

Engineering Contradiction:
Improveprocessing timeVSAvoidaddress management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The storage device is segmented into distinct address ranges, with each range dedicated to a specific data type. This segmentation allows the system to track data types through range identifiers rather than individual addresses, reducing address management complexity and processing time while maintaining data type separation.

Inventive Principle:
Principle #1Segmentation

2Productivity

If contiguous address ranges are assigned for different data types, then data retrieval efficiency improves, but address space utilization may be reduced due to allocation of continuous blocks

Engineering Contradiction:
Improvedata retrieval efficiencyVSAvoidaddress space utilization
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The address space is segmented into contiguous ranges allocated to different data types. Each data type receives a continuous block of addresses, enabling efficient retrieval through range-based addressing while the segmentation ensures systematic utilization of the available address space.

Inventive Principle:
Principle #1Segmentation

3Reliability

If a common memory cache stores all data types, then cache hit rate improves, but cache management complexity increases due to the need to manage diverse data types in a single cache

Engineering Contradiction:
Improvecache hit rateVSAvoidcache management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The common memory cache is segmented into multiple cache portions, with each portion dedicated to storing a specific data type. This segmentation enables the cache to achieve high hit rates by keeping related data types in the same cache while simplifying management through type-specific organization rather than handling all data types uniformly.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A single common memory cache structure serves multiple data types simultaneously through its segmented portions. This universal cache design improves overall system reliability by providing a unified cache hit mechanism while the internal segmentation manages the complexity of storing diverse data types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9047686B2Data storage address assignment for graphics processing
Publication Date: 2015.06.02 QUALCOMM INC
  • US9047686B2 patent drawing
  • US9047686B2 patent drawing
  • US9047686B2 patent drawing

AI summary

In general, aspects of this disclosure describe example techniques for efficient storage of data of various data types for graphics processing. In some examples, a processing unit may assign first and second contiguous range of addresses for a first and second data type, respectively. The processing unit may store at least one of graphics data of the first or second data type or addresses of the graphics data of the first or second data type within blocks whose addresses are within the first and second contiguous range of addresses, respectively. The processing unit may store, in cache lines of a cache, the graphics data of the first data type, and the graphics data of the second data type.