Graphics Thread Dispatch Throttling for Stall-Aware Core Scheduling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing graphics processing technologies face challenges in efficiently managing resource-intensive operations such as ray tracing and rasterization, particularly in real-time applications, due to high computational demands and inefficiencies in thread dispatch and workload management.

Innovation Solution

Implementing a thread dispatch throttle control mechanism that dynamically adjusts the dispatch of threads based on workload demands, utilizing a graphics processor architecture with heterogeneous cores and specialized units for ray tracing and matrix operations, including ray tracing units and tensor cores, to optimize performance and reduce resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If thread dispatch is increased to handle more ray tracing and rasterization operations, then processing throughput is improved, but resource utilization becomes inefficient and power consumption increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements dynamic thread dispatch throttling that adjusts the rate of thread dispatch based on real-time workload conditions. When the workload queue exceeds a threshold, the dispatch rate is reduced to prevent over-provisioning and excessive power consumption. This dynamic adjustment allows the system to maintain high throughput when needed while conserving energy during low-utilization periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms by monitoring the workload queue depth and using this information to control the thread dispatch rate. The feedback loop compares the current queue depth against thresholds and adjusts dispatch throttling accordingly, ensuring that processing throughput is optimized without causing unnecessary power consumption from over-utilization.

Inventive Principle:
Principle #23Feedback

2Speed

If more threads are dispatched to improve real-time performance, then processing speed is improved, but resource utilization becomes unbalanced

Engineering Contradiction:
Improveprocessing speedVSAvoidresource utilization efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent applies partial action by dispatching only the necessary number of threads based on current workload demands rather than continuously dispatching maximum threads. The throttling mechanism ensures that threads are dispatched partially (at a controlled rate) when the workload queue is within acceptable ranges, preventing resource waste while maintaining adequate processing speed.

Inventive Principle:
Principle #16Partial or excessive action

3Loss of energy

If thread dispatch is throttled to reduce power consumption, then energy efficiency is improved, but processing throughput decreases

Engineering Contradiction:
Improveenergy efficiencyVSAvoidprocessing throughput
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The system changes the dispatch parameter (thread dispatch rate) dynamically based on workload conditions. When energy efficiency is prioritized and workload is low, the dispatch rate parameter is reduced. When throughput requirements increase, the parameter is adjusted upward. This parameter change strategy allows the system to optimize between energy efficiency and processing throughput based on real-time conditions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250355670A1Apparatus and method for thread dispatch throttle control
Publication Date: 2025.11.20 INTEL CORP
  • US20250355670A1 patent drawing
  • US20250355670A1 patent drawing
  • US20250355670A1 patent drawing

AI summary

Apparatus and method for thread dispatch throttle control. For example, an example processor comprises: a plurality of graphics cores to execute instructions of a plurality of compute threads; and dispatch circuitry to dispatch each compute thread for execution on a graphics core of the plurality of graphics cores, the dispatch circuitry to track a number of compute threads of the plurality of compute threads dispatched to each graphics core of the plurality of graphics cores which have not completed; the dispatch circuitry to adjust a dispatch throttling threshold value based on stall metrics associated with each graphics core of the plurality of graphics cores, the stall metrics including a number of cycles for which the one or more compute threads of the plurality of compute threads are stalled within a clock window.