Graphics Processor Dynamic Voltage and Frequency Scaling
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Solution Overview
Problem
Current graphics processors rely on static clock control and large granularity power management, which degrades performance while attempting to reduce power consumption, necessitating a dynamic clock or voltage control and fine-grain circuitry adjustments for effective power saving without performance loss.
Innovation Solution
A single chip 3D and 2D graphics processor employs a feedback loop with the host processor to dynamically adjust frequencies and voltage levels based on workload, incorporating auto block-level clock gating, independent frequency scaling of vertex and pixel pipes, and voltage scaling or shutdown of unused blocks to optimize power control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If static clock control and large granularity circuitry blocks are used, then power consumption is reduced, but performance is degraded
Solution Approach 1:
The graphics processor is divided into multiple independent circuitry blocks including vertex processing blocks, geometry processing blocks, and pixel processing blocks. Each block can be independently controlled with its own clock signal, allowing selective clock gating of individual blocks based on workload requirements rather than controlling the entire processor as one unit.
Solution Approach 2:
The system implements dynamic clock control where clock signals are adjusted in real-time based on actual processing needs. The clock control logic monitors activity signals from each circuitry block and dynamically gates clocks to specific blocks that are currently active, transitioning between powered-down mode and operational mode based on workload demands.
2Loss of energy
If clocks are turned off to entire blocks in power saving mode, then power consumption is reduced, but performance recovery is slow
Solution Approach 1:
By segmenting the processor into smaller independent blocks with separate clock controls, the system can maintain clocks to blocks that need immediate processing while gating clocks only to blocks that are currently inactive. This selective approach avoids the performance recovery delay associated with restarting clocks to entire large blocks.
Solution Approach 2:
Different clock control strategies are applied to different circuitry blocks based on their specific workload requirements. Active blocks receive continuous clock signals to maintain full performance, while inactive blocks have clocks gated to save power. This localized control allows performance-critical blocks to respond immediately without waiting for global power mode transitions.
3Productivity
If fine-grain circuitry clock adjustment is implemented, then performance is maintained, but device complexity increases
Solution Approach 1:
Each circuitry block includes activity detection logic that automatically generates activity signals indicating whether the block is currently processing data. The clock control logic uses these self-generated signals to automatically enable or disable clocks to appropriate blocks without requiring complex external control mechanisms, allowing the system to self-regulate power and performance.
Data Source
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AI summary
An apparatus and method is provided for data processing where power is automatically controlled with a feed back loop with the host processor based on the internal work load characterized by performance counters. The host automatically adjusts internal frequencies or voltage level to match the work load. The feedback loop allows tuning of frequency or voltage controlling power dissipation.