Graphics Controller Frame Buffer Synchronization
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Solution Overview
Problem
Current methods for synchronizing audio, video, and graphics signals often require expensive dedicated hardware and are not frame-accurate, lacking portability and platform compatibility, and cannot integrate signals in a standard PC output.
Innovation Solution
A system that uses a standard graphics display controller to output synchronized audio, video, and graphics data, with signal processing circuitry to add or discard frames as needed to maintain frame accuracy, allowing for integration of signals in various formats without specialized hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If specialized graphics controller hardware is used to synchronize signals, then synchronization accuracy is improved, but device cost and complexity increase
Solution Approach 1:
The patent uses a frame buffer as an intermediary storage element between the graphics controller and display device. The frame buffer temporarily stores frame data and allows the system to achieve frame-accurate synchronization by controlling when frames are read from and written to the buffer, without requiring complex synchronized hardware across all components.
Solution Approach 2:
The system performs preliminary actions by pre-rendering and storing complete frames in the frame buffer before display. This allows the graphics controller to operate independently at its own clock rate while the display device can be synchronized to read complete frames at the required rate, achieving frame-accurate output without synchronized hardware.
2Device complexity
If time-based correction is used to synchronize signals, then hardware complexity is reduced, but frame accuracy is lost
Solution Approach 1:
The system dynamically controls the frame buffer operations by adjusting the timing of frame reads and writes based on the desired output frame rate. The graphics controller can operate at a fixed high rate and the frame buffer dynamically selects and outputs frames at the required lower synchronized rate, maintaining frame accuracy without complex hardware.
Solution Approach 2:
The patent changes the parameter of frame output timing by controlling when frames are read from the frame buffer. By adjusting the read timing parameters of the frame buffer, the system can output frames at different rates while maintaining frame-accurate synchronization, without requiring hardware changes or time-based correction methods.
3Adaptability or versatility
If standard graphics controller is used without specialized hardware, then portability and compatibility are improved, but frame-accurate synchronized output cannot be achieved
Solution Approach 1:
The frame buffer serves multiple functions: it acts as both a standard graphics memory element and a synchronization mechanism. By making the frame buffer multi-functional, the system achieves frame-accurate synchronized output using only a standard graphics controller, enabling universal compatibility across different platforms while maintaining frame accuracy.
4Reliability
If frames are repeated or dropped to achieve synchronization, then signal synchronization is improved, but frame accuracy is lost
Solution Approach 1:
The system uses feedback by monitoring the frame buffer contents and controlling the read timing based on the desired output rate. The frame buffer receives frames at a high rate and selectively outputs frames at the synchronized lower rate, providing feedback control that maintains both synchronization and frame accuracy without repeating or dropping frames.
Data Source
AI summary
According to one aspect, the invention provides an apparatus for converting data encoded in a graphics signal to at least one output signal. The apparatus includes an input, a plurality of outputs, signal processing circuitry and a controller. The input is adapted to receive the graphics signal where the graphics signal includes a plurality of frames generated at least in part from original data. The signal processing circuitry is adapted to locate, in the graphics signal, data corresponding to the original data, convert the data corresponding to the original data to output data and communicate the output data to the plurality of outputs. The controller is adapted to monitor a capacity of the signal processing circuitry and generate a signal that results in at least one disposable frame being added to the plurality of frames. The signal processing circuitry is adapted to discard the at least one disposable frame.