Graphics Instruction Cache Scheduling Circuitry

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Solution Overview

Problem

Graphics processing units (GPUs) face challenges in efficiently scheduling instructions for execution across different types of execution units due to limited information available for scheduling circuitry, leading to inefficiencies in dispatching instructions and potential increased power consumption.

Innovation Solution

Implementing a graphics unit with multiple execution units that store decoded instructions and their characteristics in an instruction cache, allowing scheduling circuitry to select and dispatch instructions based on stored information, improving scheduling efficiency and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional scheduling circuitry is used without storing instruction characteristics, then device complexity is reduced, but scheduling efficiency and productivity deteriorate

Engineering Contradiction:
Improvescheduling efficiencyVSAvoidinstruction cache complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-storing instruction characteristics (such as execution unit type requirements, latency, throughput) in the instruction cache before scheduling decisions are made. This allows the scheduling circuitry to quickly retrieve and use this information for efficient instruction dispatch without performing complex analysis at scheduling time, thus improving productivity while maintaining reasonable device complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The instruction cache acts as an intermediary between the instruction fetch/decode stage and the scheduling circuitry. It stores decoded instructions along with their characteristics, mediating the information flow and providing the scheduling unit with pre-processed instruction metadata. This intermediary structure enables efficient scheduling by separating instruction decoding from scheduling decisions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If instruction characteristics are stored and processed, then scheduling precision is improved, but use of energy increases

Engineering Contradiction:
Improvescheduling precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts only the essential instruction characteristics needed for scheduling (such as execution unit type, latency, throughput) and stores them in the instruction cache, rather than processing or storing complete instruction details. This selective extraction approach improves scheduling precision by focusing on relevant parameters while minimizing the energy required to store and process instruction information.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If multiple execution units are implemented, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveexecution unit diversityVSAvoidgraphics unit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The instruction cache serves multiple functions: it stores decoded instructions, caches instruction characteristics, and provides scheduling information to multiple different execution units. This multi-functional design enables the system to support diverse execution units (different types with different capabilities) while using a single unified cache structure, thus improving adaptability without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10324726B1Providing instruction characteristics to graphics scheduling circuitry based on decoded instructions
Publication Date: 2019.06.18 APPLE INC
  • US10324726B1 patent drawing
  • US10324726B1 patent drawing
  • US10324726B1 patent drawing

AI summary

Techniques are disclosed relating to scheduling graphics instructions for execution on different types of execution units based on characteristics of decoded and cached graphics instruction. In some embodiments, a graphics unit includes multiple different types of execution units that are configured to execute different types of instructions (e.g., different units for datapath, sample, load/store, etc.). In some embodiments, the graphics unit stores decoded instructions in an instruction cache in at least one cache level, along with information specifying characteristics of the instructions. The characteristics may be stored at clause granularity and may indicate the type of instructions in each clause (e.g., corresponding to which type of execution unit is configured to execute the instructions). In some embodiments, scheduling circuitry is configured to access the information and select instructions from the instruction cache to send to ones of the plurality of execution units based on the stored information.