Out-of-Order Graphics L2 Cache with Side and Take Pools

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Solution Overview

Problem

Conventional second-level (L2) caches in graphics processing units are limited by their requirement to return data in the requested order, leading to delays and inefficiencies when handling out-of-order requests, particularly in multi-texture cache scenarios where subsequent hits are stalled behind earlier misses.

Innovation Solution

The implementation of an L2 cache system that utilizes auxiliary memories, such as a side pool and take pool, to manage out-of-order requests by treating subsequent requests as hits and storing them until the previous request's data is retrieved, allowing for immediate servicing of hits and reducing wait times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the L2 cache services requests in order, then data consistency is maintained, but subsequent hit requests are stalled behind earlier miss requests

Engineering Contradiction:
Improvedata consistencyVSAvoidrequest wait time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic request handling by introducing multiple output ports and a request manager that can dynamically select which requests to service based on current cache state and request characteristics, allowing the system to adapt between in-order and out-of-order servicing

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The L2 cache is segmented into multiple independent output ports (first output port, second output port) that can simultaneously service different requests, breaking the monolithic request handling into parallel independent channels that don't block each other

Inventive Principle:
Principle #1Segmentation

2Productivity

If the L2 cache uses complicated logic to reorder requests, then request efficiency is improved, but device complexity increases

Engineering Contradiction:
Improverequest servicing efficiencyVSAvoidreorder logic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A request manager acts as an intermediary component that receives requests from multiple texture caches, manages the request queue, and coordinates with output ports. This intermediary simplifies the overall system by centralizing the intelligence needed for out-of-order servicing without requiring complex logic distributed throughout the cache structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system uses dynamic request routing where the request manager can dynamically determine which requests are ready to be serviced and direct them to appropriate output ports based on current cache state, avoiding the need for static complex reorder logic

Inventive Principle:
Principle #15Dynamics

3Reliability

If the L2 cache artificially slows hit response, then request ordering is maintained, but cache utilization decreases

Engineering Contradiction:
Improverequest orderingVSAvoidcache utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Multiple output ports are introduced to segment the request servicing function, allowing different requests (hits and misses) to be handled simultaneously through different ports, eliminating the need to slow down hit responses to maintain ordering

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7565490B1Out of order graphics L2 cache
Publication Date: 2009.07.21 NVIDIA CORP
  • US7565490B1 patent drawing
  • US7565490B1 patent drawing
  • US7565490B1 patent drawing

AI summary

Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that are misses to be returned from a graphics memory. A first auxiliary memory, referred to as a side pool, is used for holding subsequent requests for data at a specific address while a previous request for data at that address is serviced by a frame buffer interface and graphics memory. This L2 cache may also use a second auxiliary memory, referred to as a take pool, to store requests or pointers to data that is ready to be retrieved from an L2 cache.