Graphics Memory Abandonment for Near Memory Allocation

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Solution Overview

Problem

In two-level memory systems, memory regions allocated to latency-sensitive operations like graphics processing are persistently held in cache memory to ensure performance, but this leads to system overhead and inefficient use of near and far memory resources, causing performance impacts on other tasks and unnecessary occupation of limited near memory resources.

Innovation Solution

Implementing a mechanism where the graphics driver can declare memory regions as abandoned, allowing the cache controller to forget their contents and overwrite them, and dynamically allocate memory between cache and graphics regions without writing back data to main memory, enabling more efficient use of near and far memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory regions are persistently held in cache memory to ensure graphics processing performance, then graphics processing performance is improved, but near memory resources are unnecessarily occupied and system overhead increases

Engineering Contradiction:
Improvegraphics processing performanceVSAvoidnear memory resource occupation
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent implements dynamic memory management where the graphics driver can declare memory regions as abandoned, allowing the cache controller to dynamically allocate and deallocate cache memory based on actual needs. This transforms the static persistent holding approach into a dynamic system that adapts to changing graphics processing requirements, freeing near memory resources when not currently needed while maintaining performance when required.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent enables the graphics driver to discard memory regions by declaring them abandoned, allowing the cache controller to recover and reallocate these memory regions for other purposes. This discarding and recovering mechanism eliminates the need to permanently hold memory regions in cache, resolving the contradiction between maintaining performance and freeing resources.

Inventive Principle:
Principle #34Discarding and recovering

2Speed

If memory regions are persistently held in cache memory to ensure graphics processing performance, then graphics processing performance is improved, but system overhead increases

Engineering Contradiction:
Improvegraphics processing performanceVSAvoidsystem overhead
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements a self-service mechanism where the graphics driver autonomously manages memory region allocation and abandonment without requiring complex system-wide coordination. The cache controller responds to simple abandonment declarations from the driver, eliminating the need for complex bookkeeping and coordination protocols, thereby reducing system overhead while maintaining performance.

Inventive Principle:
Principle #25Self-service

3Speed

If cache memory is allocated to graphics region with no corresponding mapping in main memory, then near memory usage is optimized for graphics performance, but far memory availability for other tasks is reduced

Engineering Contradiction:
Improvenear memory access speedVSAvoidfar memory availability
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent creates a dynamic relationship between near and far memory through the abandonment mechanism. When graphics memory is abandoned, the cache controller can reallocate those cache lines for far memory mapping, dynamically balancing near memory optimization for graphics with far memory availability for other tasks based on current system needs.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10304418B2Operating system transparent system memory abandonment
Publication Date: 2019.05.28 INTEL CORP
  • US10304418B2 patent drawing
  • US10304418B2 patent drawing
  • US10304418B2 patent drawing

AI summary

An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.