Graphics Pipeline Stage Subsets for Latency Reduction

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Solution Overview

Problem

Existing graphics processing systems are limited in their ability to efficiently control and utilize subsets of the graphics processing pipeline, leading to increased latency and resource inefficiencies, particularly in tile-based graphics processing systems for virtual reality displays.

Innovation Solution

The system allows applications to request and control graphics processing operations using specific subsets of the graphics processing pipeline stages, enabling independent activation and execution of these stages, thereby decoupling the pipeline into manageable parts for optimized resource allocation and reduced latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the entire graphics processing pipeline is activated for all rendering operations, then complete graphics processing functionality is achieved, but latency increases and resource utilization decreases for operations that don't require all stages

Engineering Contradiction:
Improverendering efficiencyVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The graphics processing pipeline is divided into distinct addressable stages including vertex processing, primitive assembly, tiling, and fragment processing. Each stage can be independently activated based on the specific rendering operation requirements, allowing the system to process only the necessary portions of the pipeline rather than executing all stages for every operation.

Inventive Principle:
Principle #1Segmentation

2Reliability

If all pipeline stages are executed for every graphics operation, then comprehensive processing is ensured, but resource utilization becomes inefficient

Engineering Contradiction:
Improveprocessing completenessVSAvoidresource utilization
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The pipeline configuration is made dynamic and adaptable through driver-controlled stage activation. The system can adjust which pipeline stages are executed based on the specific rendering task, transitioning between different operational modes (full pipeline, subset pipeline, or alternative pipeline paths) to optimize resource utilization while maintaining processing completeness for each operation type.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If the graphics processing pipeline is used for all rendering tasks including geometry processing, then unified processing is achieved, but the load on the graphics processor increases unnecessarily

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidprocessor load
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Geometry processing functions are extracted from the graphics processing pipeline and assigned to the host processor. The graphics processor pipeline is configured to receive already-processed geometry data, eliminating the need for vertex processing and primitive assembly stages to execute on the graphics processor itself, thereby reducing its computational load while maintaining unified rendering capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10803547B2Graphics processing systems using a subset of pipeline stages
Publication Date: 2020.10.13 ARM LTD
  • US10803547B2 patent drawing
  • US10803547B2 patent drawing
  • US10803547B2 patent drawing

AI summary

In a graphics processing system, an application executing on a host processor can request graphics processing operations that are to be performed by only subsets of the set of stages of a graphics processing pipeline implemented by a graphics processor. In response to such a request, the driver for the graphics processor causes the graphics processing operation that is to be performed using only a subset of the set of stages of the graphics processing pipeline to be performed. The driver can cause the graphics processing operation that is to be performed by the subset of stages of the graphics processing pipeline to be performed by the graphics processor, or on the host processor.