Graphics Processor Blocking Circuit for Overlapping Memory Deallocation
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Solution Overview
Problem
Current graphics processors experience latency due to memory recycling at the end of a fragment kick and require time for housekeeping functions, limiting the ability to overlap memory deallocation with fragment processing of the next task.
Innovation Solution
A graphics processor is designed with geometry and fragment processing logic that allows for overlapping of memory deallocation with the processing of subsequent tasks, using a memory management circuit to track memory regions and a blocking circuit to prevent premature deallocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory deallocation is performed at the end of a fragment kick, then memory management correctness is ensured, but processing latency increases and productivity decreases
Solution Approach 1:
The patent applies preliminary action by allowing the fragment processing pipeline to begin processing the next task before the memory deallocation of the previous task is complete. The blocking circuit prevents premature access to memory regions that are still being deallocated, ensuring correctness while enabling overlapping operations. This resolves the contradiction by performing memory deallocation in advance of when it would traditionally block subsequent processing.
2Productivity
If memory deallocation is overlapped with fragment processing, then productivity improves, but the risk of accessing deallocated memory increases
Solution Approach 1:
The blocking circuit serves as an intermediary mechanism that mediates between the fragment processing logic and the memory management circuit. It receives indicators from the memory management circuit about ongoing deallocation operations and uses these to control access by the fragment processing logic. This intermediary ensures that processing can overlap with deallocation while preventing unsafe access to memory regions that are still being freed.
3Reliability
If a blocking circuit is implemented to prevent premature deallocation, then memory access safety is ensured, but device complexity increases
Solution Approach 1:
The blocking circuit is implemented as a segmented, modular component that integrates into the existing graphics processor architecture. It is divided into distinct functional units: a first blocking circuit for geometry processing logic and a second blocking circuit for fragment processing logic. Each blocking circuit receives specific indicators from the memory management circuit and controls access for specific processing logic, reducing overall complexity through functional segmentation.
4Reliability
If memory deallocation waits for all spatial units to be processed, then memory management correctness is ensured, but loss of time increases
Solution Approach 1:
The patent applies preliminary action by initiating memory deallocation operations before the fragment processing of all spatial units is complete. The memory management circuit begins deallocating memory regions as soon as the associated spatial units have been processed, rather than waiting for all spatial units across all tasks to be processed. This reduces deallocation latency while maintaining correctness through the blocking circuit's safety mechanisms.
Data Source
AI summary
A processor includes a first processing pipeline, a second processing pipeline and a memory management that allocates memory regions from memory for the first processing pipeline to write the data of each of a first of a sequence of tasks, and deallocates each of the memory regions after the data therein has been processed by the second processing pipeline. A blocking circuit enables the second processing pipeline to start processing a second sequence of tasks while the memory management circuit is still deallocating some of the memory regions allocated to the data portions of the first of said sequence of tasks, the blocking circuit preventing identifiers of the data portions of the second task being passed to the memory management circuit until the memory management circuit indicates that it has completed deallocating the memory regions allocated to all the data portions of the first task.