Graphics Processor Sequencer for Multi-Core Resource Management
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Solution Overview
Problem
Symmetric multiprocessing architectures in graphics processor platforms are not always suitable for efficient resource management, particularly in multi-core central processor systems, leading to suboptimal performance and latency in data display systems, especially in aircraft cockpits.
Innovation Solution
A graphics processor with reserved storage space for N sets of descriptors and a sequencer that processes these descriptors successively, allowing direct resource sharing at the graphics processor level rather than relying on the operating system, enabling operation under asymmetric multiprocessing architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If symmetric multiprocessing architecture is used with operating system managing resources, then system compatibility and ease of operation are improved, but resource management efficiency and latency are worsened
Solution Approach 1:
The patent segments the resource management function by creating separate descriptor sets in the graphics processor's storage space for each CPU core. Each core has its own dedicated descriptor set (first descriptor set for first core, second descriptor set for second core, etc.), allowing independent resource management per core while maintaining overall system compatibility.
Solution Approach 2:
The patent introduces an intermediary mechanism at the graphics processor level between the operating system and resource allocation. The sequencer and descriptor sets act as intermediaries that translate high-level OS resource requests into low-level hardware resource allocations, enabling efficient direct resource sharing while preserving OS-level compatibility.
2Device complexity
If operating system manages graphics processor resources, then system simplicity is maintained, but latency in resource access increases
Solution Approach 1:
The patent implements preliminary action by pre-allocating and preparing descriptor sets in the graphics processor's storage space before resource access is needed. Each CPU core has its descriptor set ready in advance, allowing immediate resource access without waiting for OS-mediated allocation, thus reducing latency while maintaining system simplicity.
Solution Approach 2:
The graphics processor performs self-service resource management through its dedicated sequencer and descriptor sets. Each core can directly access its own descriptor set without requiring continuous OS intervention, enabling autonomous resource allocation and reducing access latency while keeping the overall system simple.
3Productivity
If direct resource sharing at graphics processor level is implemented, then resource management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent achieves universality by designing a multi-functional descriptor set structure that serves multiple purposes: resource allocation, commandqueuing, and core-specific resource tracking. The same descriptor set infrastructure handles all resource management tasks for multiple cores, improving efficiency without proportionally increasing complexity.
Solution Approach 2:
The patent applies nesting by organizing resource management structures within the graphics processor itself. The descriptor sets are nested within the graphics processor's internal storage space, and the sequencer is nested within the resource management unit, creating a hierarchical structure that improves efficiency while containing complexity within modular sub-components.
Data Source
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AI summary
This graphics processor (18) is intended to be connected to a multicore central processor (16) having N distinct cores (Ci, C2), where N is an integer greater than or equal to 2, and includes a memory (26). The memory (26) comprises a reserved space (40) for storing N sets (42) of descriptor(s) (44), each set (42) of descriptor(s) (44) being associated with a respective core (Ci, C2) of the multicore central processor (16), each descriptor (44) identifying a set of resources of the graphics processor (18) for displaying data by a software application intended to be executed via said core (Ci, C2). The graphics processor (18) further includes a sequencer (28) configured to process successively the descriptors (44) stored in the reserved storage space (40).