Graphics Processor Thread Scheduling for Sensor-Coordinated Inference

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional graphics processing techniques do not effectively coordinate inference output with sensor inputs, leading to inaccuracies and underutilization of graphics processors during inference operations.

Innovation Solution

A novel technique involving a finite state machine that facilitates the detection of frequently-used data values and employs lookup tables and reduced math operations to optimize graphics processor utilization, coupled with a GPU that accelerates graphics and machine-learning operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional techniques are used for graphics processing, then the graphics processor can handle basic graphics operations, but the processor remains underutilized during inference operations with light workload

Engineering Contradiction:
Improvegraphics processor utilizationVSAvoidwasted processing capacity
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent extends the graphics processor's functionality beyond traditional graphics operations to include machine learning inference operations. By making the graphics processor universal capable of both graphics rendering and neural network inference, the system fully utilizes the processor's capacity during inference tasks, preventing the underutilization described in the contradiction.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If conventional techniques are used for inference processing, then the graphics processor can perform inference operations, but coordination between inference output and sensor inputs is lacking leading to accuracy issues

Engineering Contradiction:
Improveinference output accuracyVSAvoidcoordination mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where inference outputs are coordinated with sensor inputs. The system uses the inference results to adjust and optimize subsequent sensor data processing, creating a closed-loop system that continuously improves accuracy by leveraging the interaction between inference outputs and sensor inputs.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If traditional graphics processing methods are used, then the system can process graphics data, but inference accuracy is compromised due to lack of coordination with sensor inputs

Engineering Contradiction:
Improveinference accuracyVSAvoidprocessing coordination
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent merges the graphics processing pipeline with sensor input processing and inference operations. By combining these previously separate functions into an integrated system, the patent achieves coordinated processing that improves inference accuracy while maintaining operational simplicity through unified data flow management.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4325424B1Coordination and increased utilization of graphics processors during inference
Publication Date: 2025.09.03 INTEL CORP
  • EP4325424B1 patent drawingFigure 1
  • EP4325424B1 patent drawingFigure 2A
  • EP4325424B1 patent drawingFigure 2B

AI summary

A method of embodiments, as described herein, includes scheduling resources in a system for a plurality of contexts, the resources of the system including multiple streaming processors; specifying a portion of available threads as a limitation on usage of the multiple streaming processors; and upon determining that the limitation on usage of the multiple streaming processors is set, limiting usage of the multiple streaming processors by one or more contexts of the plurality of contexts. Limiting usage of the multiple streaming processors includes limiting threads for the one or more contexts to the specified portion of available threads of the multiple streaming processors, the specified portion being less than all available threads of the multiple streaming processors. Limiting threads for the one or more contexts to the specified portion of available threads includes limiting the one or more contexts to a subset of the multiple streaming processors, the subset being less than all available streaming processors.