Graphics Scheduler Double-Buffered Queue Submission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In graphics processing systems, existing scheduling methods often lead to idle hardware periods due to the submission of work items in batches, causing pre-emption of ongoing tasks when new work queues are written, which can prevent low power states and reduce efficiency.
Innovation Solution
A double-buffered submission and execution queue system that allows for explicit submission of work items without automatic pre-emption, enabling continuous operation and efficient power management by allowing partial queues and fine-grained interrupt control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If work items are submitted in batches to the graphics processing subsystem, then the submission process is simplified, but it causes idle hardware periods and pre-emption of ongoing tasks
Solution Approach 1:
The patent segments the workload submission process by introducing a command ring buffer that separates command submission from execution. Commands are queued in the ring buffer and executed continuously without pre-emption, allowing batch submission while maintaining processing continuity. The ring buffer is divided into head and tail pointers that enable efficient queue management without interrupting ongoing graphics tasks.
Solution Approach 2:
The patent implements preliminary action by pre-allocating and pre-configuring the command ring buffer structure before workload submission. The buffer is prepared with proper memory allocation and pointer initialization, allowing workloads to be submitted directly without dynamic memory management during execution. This preliminary setup eliminates the need for real-time queue restructuring that would cause pre-emption.
2Extent of automation
If the general-purpose processor schedules operations for the graphics processing system, then scheduling control is centralized, but the processor cannot enter low power states due to repeated interrupts
Solution Approach 1:
The patent extracts the scheduling control function from the general-purpose processor and implements it within the graphics processing subsystem itself. The command ring buffer and its associated management logic are integrated into the graphics subsystem, allowing it to autonomously manage its own command queue without requiring continuous processor intervention. This extraction enables the processor to enter low power states while the graphics subsystem continues autonomous operation.
Solution Approach 2:
The graphics processing subsystem implements self-service by autonomously managing its command queue through the ring buffer mechanism. The subsystem can independently add commands to the queue, manage buffer pointers, and execute commands without external processor intervention. This self-service capability reduces the frequency of processor interrupts and allows the processor to conserve energy through low power states.
3Productivity
If a new work queue is written while hardware is processing previous work, then the processor can efficiently manage multiple tasks, but it causes pre-emption of currently running work items
Solution Approach 1:
The patent ensures continuity of useful action by implementing a single continuous command ring buffer that maintains an unbroken sequence of commands. New work items are appended to the tail of the buffer while the head pointer continuously processes existing commands without interruption. This continuous action approach allows multiple tasks to be managed efficiently while preserving the stability and continuity of execution, eliminating pre-emption of running work items.
Data Source
AI summary
Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.