Graphics Surface Addressing via Multi-Layer Translation
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Solution Overview
Problem
Graphics processors face memory allocation challenges when handling large graphics surfaces, as allocating memory for entire surfaces can negatively impact other processing tasks and lead to bandwidth and allocation issues.
Innovation Solution
Implementing a multi-layer address translation system that allows graphics surfaces to use sparse memory allocation, where surfaces have their own unique surface space mapped to virtual space using a translation table, enabling efficient access without allocating memory for the entire surface, and utilizing translation circuitry to handle addresses in surface, virtual, and physical spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory space is allocated for entire graphics surfaces, then graphics processing can proceed, but bandwidth and allocation are negatively impacted
Solution Approach 1:
The patent segments the graphics surface memory allocation into two distinct spaces: surface space (logical addressing space) and storage space (physical memory allocation). This segmentation allows the surface to be addressed as if fully allocated while actually storing only the portions of data that are currently needed, thereby reducing bandwidth consumption without compromising graphics processing reliability.
Solution Approach 2:
The patent introduces a translation circuit as an intermediary between the surface space and storage space. This translation circuit performs address translation, converting surface space addresses to storage space addresses, enabling the system to maintain large surface addresses for graphics processing while physically allocating minimal memory, thus resolving the bandwidth conflict.
2Reliability
If memory space is allocated for entire graphics surfaces, then graphics processing can proceed, but allocation is negatively impacted
Solution Approach 1:
The patent divides the memory management into surface space (logical) and storage space (physical), allowing the system to present a large addressable surface space to graphics processing while physically allocating only the necessary portions in storage space. This segmentation enables full graphics processing functionality without requiring full surface memory allocation.
Solution Approach 2:
The patent adds an address translation dimension between surface space and storage space. By introducing this intermediate translation layer, the system can support large surface addresses (4GB or more) while physically using minimal memory, effectively resolving the allocation conflict through dimensional transformation of the address space.
3Loss of energy
If sparse memory allocation is used for graphics surfaces, then bandwidth and allocation are optimized, but address translation complexity increases
Solution Approach 1:
The patent introduces a dedicated translation circuit as an intermediary to handle the complexity of address translation. This specialized hardware component manages the mapping between surface space and storage space, isolating the translation complexity from the rest of the graphics processing system and enabling sparse memory allocation without burdening the main processing logic.
4Quantity of substance
If sparse memory allocation is used for graphics surfaces, then allocation is optimized, but system complexity increases
Solution Approach 1:
The patent segments the memory system into surface space and storage space with a dedicated translation circuit. This segmentation allows the system to use minimal physical memory allocation while maintaining large logical surface addresses, with the translation circuit handling the complexity of mapping between the two spaces, thus optimizing memory usage without overwhelming the system architecture.
Solution Approach 2:
By adding the address translation dimension, the patent enables the system to support large surface spaces (e.g., 4GB or more) while using minimal physical memory. The translation circuit operates in this intermediate dimensional space, resolving the conflict between large logical allocation and small physical allocation without significantly increasing overall system complexity.
Data Source
AI summary
Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.