Graphics Processor Tile Buffering for Bus Traffic Reduction
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Solution Overview
Problem
Current vector graphics systems face challenges in buffer management, particularly in compact hardware implementations, due to large memory requirements for sub-pixel counter values, leading to increased bus traffic between graphics accelerators and main memory, which is impractical for mobile devices with limited bandwidth.
Innovation Solution
Implementing a graphics processor with internal buffers and determination logic to store and manage counter values efficiently, allowing for reduced bus traffic by using internal memory for counter information and minimizing external memory access, enabling processing in tiles rather than the entire screen, thus reducing memory allocation and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If counter values for each sub-pixel are stored in external main memory, then sufficient storage capacity is available, but bus traffic between graphics accelerator and main memory increases significantly
Solution Approach 1:
The patent divides the screen into multiple tiles and processes each tile independently. For each tile, only the counter values needed for that specific tile are loaded into the graphics accelerator's internal memory from external main memory. This segmentation reduces the amount of data transferred over the bus at any given time, while still providing sufficient storage capacity through the combination of internal and external memory resources.
2Reliability
If a large buffer is implemented in graphics hardware accelerator, then counter values can be stored internally, but manufacturing cost and device complexity increase
Solution Approach 1:
Instead of implementing a complete buffer for the entire screen in the graphics hardware accelerator, the patent implements a smaller internal buffer that can hold counter values for only a portion of the screen (one tile at a time). This partial buffer is sufficient for the rendering operations needed, avoiding the excessive cost and complexity of a full-screen buffer while maintaining the reliability of internal storage for active processing.
3Quantity of substance
If more memory is added to graphics hardware accelerator, then buffer size increases, but device size and power consumption increase
Solution Approach 1:
The patent implements a dynamic memory allocation strategy where the buffer size in the graphics hardware accelerator is adjusted based on the current processing requirements. The system dynamically loads only the necessary counter values for the current tile into internal memory, and discards them after processing. This dynamic approach allows the buffer size to vary from very small (when processing one tile) to effectively large (when considering the entire screen across multiple tile processing cycles), without requiring a permanently large buffer that would consume excessive power.
Data Source
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AI summary
A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.