Graphics Tile Interleave for On-Chip Memory Reduction
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Solution Overview
Problem
Current graphics processing systems face inefficiencies in rendering graphical images due to the need for frequent access to external memory, as they write and read intermediate images, leading to increased memory traffic and unnecessary processing of intermediate data.
Innovation Solution
The method involves interleaving graphics rendering operations and compute shader operations based on dependency information, allowing intermediate results to be maintained on-chip, reducing external memory access by scheduling graphics and compute shader operations in a tile-based manner without recompiling the compute shader.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If intermediate images are written to external memory and read back for processing, then the graphics processing system can handle complex rendering operations, but memory traffic increases and processing efficiency decreases
Solution Approach 1:
The patent divides the intermediate image data into tiles that can be processed independently. By segmenting the rendering workload into tile-based units, the system can process and discard individual tiles that are not needed for subsequent operations, avoiding the energy cost of writing and reading entire intermediate images to external memory. This segmentation enables selective processing that reduces unnecessary memory traffic while maintaining rendering quality for visible portions of the scene.
2Productivity
If the graphics processor renders complete intermediate images to external memory, then all rendering operations can be performed, but the time required for memory write and read operations increases
Solution Approach 1:
The patent performs preliminary determination of which intermediate image tiles are actually needed for subsequent rendering operations before committing all data to external memory. By analyzing the render dependency information in advance, the system can identify and process only the necessary tiles, performing preliminary actions that eliminate unnecessary memory I/O operations and reduce the time required for complete rendering pipelines.
Solution Approach 2:
The patent enables the graphics processor to skip writing intermediate image tiles to external memory when those tiles are determined to be unnecessary for subsequent operations. By rushing through the rendering pipeline selectively - processing needed tiles and discarding unnecessary ones - the system avoids the time penalty of complete memory round-trips while maintaining rendering correctness for visible content.
3Area of stationary object
If intermediate rendering data is stored in external memory, then the system can handle large image sizes, but the complexity of memory management and data flow increases
Solution Approach 1:
The patent segments intermediate image storage into tile-based units with associated dependency metadata, rather than managing entire large images as monolithic blocks. This segmentation approach reduces memory management complexity by enabling independent tracking and processing of smaller tile units, where each tile's storage and retrieval can be managed separately based on its specific dependency requirements, rather than managing entire intermediate images.
Solution Approach 2:
The patent extracts and utilizes render dependency information from the rendering pipeline to guide memory management decisions. By taking out the dependency analysis function and using it to determine which intermediate tiles need external storage versus which can remain in on-chip memory or be discarded, the system simplifies overall memory management by making storage decisions based on actual rendering needs rather than conservative blanket storage of all intermediate data.
Data Source
AI summary
There is provided a method of a graphics processing system, the method including receiving dependency information for a set of interdependent images indicating a dependency across one or more compute shader and graphics workloads, and interleaving processing of the compute shader and graphics workloads for the set of interdependent images in accordance with the dependency information without recompiling a compute shader generating the one or more compute shader workloads.