Graphics Virtualization Memory Allocation for Multi-VM Performance

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Solution Overview

Problem

Existing GPU virtualization technologies face challenges in efficiently managing graphics memory access and resource sharing across multiple virtual machines, leading to performance bottlenecks and inefficiencies.

Innovation Solution

A system and method for intelligent allocation of graphics memory and cache resources between virtual machines, utilizing a virtualization architecture that includes intelligent tile caching and spillover into system memory, along with buffering and arbitration mechanisms to reduce blocking and enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If shadow page tables are implemented for GPU virtualization, then multiple VMs can share a physical GPU, but memory usage increases due to the need for additional translation structures

Engineering Contradiction:
ImproveGPU sharing capabilityVSAvoidmemory usage
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent implements shadow page tables as copies of guest page tables at the hypervisor level. These shadow page tables replicate the guest virtual address space mappings to enable address translation for multiple VMs sharing a physical GPU, while maintaining the ability to share common pages across VMs to reduce overall memory consumption.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent merges page tables from multiple VMs by identifying and combining common pages. When multiple VMs have identical or similar page table entries, the system merges these into shared pages, reducing the total memory required for shadow page tables while maintaining isolation and security between VMs.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If GPU memory is virtualized with address translation, then multiple VMs can access shared graphics memory, but access speed decreases due to translation overhead

Engineering Contradiction:
Improvememory sharing capabilityVSAvoidmemory access speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent performs preliminary address translation by pre-establishing shadow page tables that map guest virtual addresses to host physical addresses before GPU access occurs. This preliminary setup allows subsequent memory accesses to use the pre-computed shadow page tables, reducing the translation overhead during actual GPU operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces shadow page tables as an intermediary layer between guest virtual address spaces and host physical memory. This intermediary structure enables efficient address translation by caching the mapping relationships, allowing multiple VMs to access shared graphics memory with reduced translation overhead compared to direct hypervisor-mediated translation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If a single physical GPU is passed through to one VM, then performance is maximized, but resource utilization decreases when multiple VMs need GPU access

Engineering Contradiction:
ImproveGPU performanceVSAvoidresource sharing capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent segments the GPU address space into multiple virtual address spaces, each mapped to the same physical GPU resources. By dividing the address space into separate guest physical address spaces for different VMs and implementing virtualization at the address translation level, the system allows multiple VMs to simultaneously access the physical GPU with near-native performance while maintaining resource isolation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4130999B1Apparatus and method for efficient graphics virtualization
Publication Date: 2025.08.27 INTEL CORP
  • EP4130999B1 patent drawingFigure 1
  • EP4130999B1 patent drawingFigure 2
  • EP4130999B1 patent drawingFigure 3

AI summary

A processor and method are described for allocating portions of a memory interconnect to virtual machines. For example, one embodiment of a processor comprises: a first memory to store data; a plurality of multiprocessors, each multiprocessor comprising a plurality of execution resources to execute commands to process the data; a memory interconnect to couple the plurality of multiprocessors to the first memory; and allocation hardware logic to allocate a first portion of the memory interconnect to a first virtual machine, VM, and to further allocate a second portion of the memory interconnect to a second VM.