Voltage Droop Mitigation in Graphics Logic via Pipeline Bubbles
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Solution Overview
Problem
Graphics processors experience voltage droop and increased power consumption when frequency changes, leading to performance reduction and additional delays due to abrupt current changes, which existing mitigation solutions fail to adequately address.
Innovation Solution
Implementing a current change mitigation technique using programmable dynamic capacitance clamping and sensed voltage feedback to control the ramp-up of current in graphics logic, allowing for reduced voltage droop and improved power performance by inserting bubbles into EU and sampler pipelines to manage dynamic capacitance and voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the operating frequency of graphics processors is changed to control power consumption, then power consumption is reduced during idle times, but voltage droop and performance reduction occur due to abrupt current changes
Solution Approach 1:
The system performs preliminary actions by pre-charging capacitors and gradually ramping up current before the actual frequency change is completed. This preparatory current buildup ensures that when the frequency transitions, the voltage remains stable because the capacitors are already charged and ready to compensate for any voltage droop that might occur.
Solution Approach 2:
The system employs feedback mechanisms by monitoring voltage levels and current changes in real-time during frequency transitions. Based on this feedback, the control logic dynamically adjusts the charging rate of capacitors and the timing of frequency changes to prevent voltage droop, ensuring stable operation while achieving power savings.
2Productivity
If the operating frequency of graphics processors is increased to improve performance, then computational capability is enhanced, but additional delay and power consumption increase due to complex design operations required for frequency changes
Solution Approach 1:
The system performs preliminary actions by pre-charging capacitors and preparing current paths before the frequency transition begins. This head start on current buildup reduces the time needed during the actual frequency change, minimizing performance delays while still achieving the desired frequency increase for improved computational capability.
3Productivity
If abrupt current changes are allowed during frequency transitions, then power consumption is reduced and frequency switching is faster, but voltage droop increases causing performance reduction
Solution Approach 1:
The system performs preliminary current buildup by charging capacitors in advance of the frequency transition. This pre-charging action allows the system to switch frequencies quickly while maintaining voltage stability, as the capacitors are already charged and can immediately compensate for any current changes during the transition.
Solution Approach 2:
The system uses feedback to monitor voltage levels during frequency transitions and dynamically adjusts the current charging rate. This feedback control allows for faster switching by optimizing the charge/discharge timing of capacitors, while preventing voltage droop by adjusting the current profile based on real-time voltage measurements.
Data Source
AI summary
Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.