Graphite Wiring Circuit for Semiconductor Applications
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Solution Overview
Problem
Current technologies face challenges in producing graphite wiring with high electrical conductivity and carrier mobility for semiconductor applications, particularly in achieving thicknesses of 20 nm or less and maintaining high-quality properties, as well as handling graphite films with thicknesses of 300 nm or less as independent films.
Innovation Solution
A method involving the preparation of a high-quality graphite film with a thickness of 500 nm or more and less than 9.6 μm using the polymer baking method, followed by plasma etching to form a graphite thin film with a thickness of 3 nm or more and less than 300 nm, ensuring electrical conductivity of 18000 S/cm or more and carrier mobility of 9500 cm2/Vsec or more along the graphite film plane direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If graphite film thickness is reduced to 300 nm or less for fine wiring applications, then wiring resistance increases and electrical conductance decreases, but the patent achieves high electrical conductivity (18000 S/cm or more) and high carrier mobility (9500 cm2/Vsec or more) in thin graphite films (3-300 nm) through optimized preparation methods
Solution Approach 1:
The patent applies parameter changes by optimizing the preparation conditions of graphite films, including controlling thickness (3-300 nm), electrical conductivity (≥18000 S/cm), and carrier mobility (≥9500 cm2/Vsec). By precisely adjusting these parameters during film formation, the patent achieves high electrical conductance in ultra-thin graphite layers, resolving the contradiction between thinness and conductivity.
2Length of moving object
If metal wiring is miniaturized to 300 nm or less, then wiring resistance increases due to inelastic scattering of electrons at grain boundaries, but graphite wiring maintains stable resistance characteristics even at fine dimensions
Solution Approach 1:
The patent uses graphite as a composite material alternative to traditional metal wiring. Graphite's unique crystalline structure with SP2 bonding provides different conduction mechanisms that avoid the grain boundary scattering issues plaguing miniaturized metal wiring. This material substitution enables stable resistance characteristics at fine dimensions (300 nm or less) where metal wiring fails.
3Volume of moving object
If CVD method is used to form multilayer graphene for wiring, then wiring thickness can be increased, but electrical conductivity decreases due to poor crystallinity in thicker layers
Solution Approach 1:
The patent optimizes preparation parameters to achieve a critical balance between thickness and crystallinity. By controlling the graphite film thickness within the 3-300 nm range and maintaining electrical conductivity ≥18000 S/cm and carrier mobility ≥9500 cm2/Vsec, the patent identifies optimal parameter zones where both adequate thickness and high electrical conductivity coexist, avoiding the conductivity degradation seen in thicker CVD graphene.
4Volume of moving object
If graphite film is made thinner to achieve fine wiring, then handling and processing becomes difficult, but the patent enables plasma etching to form precise wiring patterns in ultra-thin graphite films
Solution Approach 1:
The patent introduces plasma etching as an intermediary process that bridges the gap between ultra-thin graphite film formation and precise wiring pattern creation. Plasma etching provides controlled material removal that enables accurate patterning of graphite films as thin as 3 nm, making thin-film graphite processing feasible and precise without direct mechanical handling of the fragile thin films.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a graphite wiring circuit with enhanced electrical conductance and current density resistance, effectively preventing sudden increases in resistance and improving heat dissipation, making it suitable for fine semiconductor wiring.
Implementation Method 1
preparation of a high-quality graphite film with a thickness of 500 nm or more and less than 9.6 μm using the polymer baking method
Implementation Method 2
preparation of a high-quality graphite film... using the polymer baking method
Implementation Method 3
followed by plasma etching to form a graphite thin film with a thickness of 3 nm or more and less than 300 nm
Data Source
AI summary
The present disclosure relates to a wiring circuit, and a method for producing the wiring circuit, that includes graphite wiring having a specified thickness, a high electrical conductivity, and a high carrier mobility. The wiring circuit may include graphite wiring comprised of graphite where the graphite wiring has a thickness of 3 nm or more and less than 300 nm. The graphite may have an electrical conductivity along a graphite film plane direction of 18000 S/cm or more, and the graphite may have a carrier mobility along the graphite film plane direction of 9500 cm2/Vsec or more. The method for producing a wiring circuit may include steps of: (1) bonding a graphite film with a substrate; (2) plasma etching the graphite film to form a graphite thin film; and (3) etching the graphite thin film to form a wiring circuit.