Grated MIM Capacitor Sidewall Trenches
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Solution Overview
Problem
On-chip metal-insulator-metal (MIM) capacitors require a large chip area to achieve minimal capacitance, leading to increased chip size and cost, necessitating a solution to enhance capacitance without expanding the chip dimensions.
Innovation Solution
The formation of MIM capacitors along the sidewall and bottom surfaces of trenches in the back-end-of-the-line metallization stack increases the surface area, allowing for enhanced capacitance without enlarging the chip size, involving a method that includes forming trenches, depositing metal layers, and patterning to create interconnect structures that contact the capacitor electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large chip area is used for planar MIM capacitor electrodes, then the capacitance is sufficient, but the chip size and cost increase
Solution Approach 1:
The patent transitions from planar (2D) capacitor electrodes to three-dimensional (3D) electrodes by forming tapered structures with increased surface area. The electrodes extend vertically and laterally with tapered sidewalls, utilizing the third dimension (height) to increase capacitance without proportionally increasing chip area. This dimensional transformation allows achieving higher capacitance density within the same footprint.
Solution Approach 2:
The capacitor structure is segmented into multiple components: upper and lower electrodes with tapered sidewalls, intermediate dielectric layers, and fill dielectric material. The tapered sidewalls create additional surface area segments that contribute to capacitance. This segmentation allows optimization of each component's geometry to maximize capacitance while minimizing area usage.
2Quantity of substance
If planar electrode plates are used to ensure minimal capacitance, then capacitance requirement is met, but the chip size increases
Solution Approach 1:
The patent employs three-dimensional tapered electrodes that extend both vertically and laterally, transforming the conventional planar structure into a volumetric structure. This allows the capacitor to achieve required capacitance through increased electrode surface area in multiple dimensions rather than expanding the chip's lateral footprint, thus reducing overall chip dimensions.
Solution Approach 2:
The capacitor structure embeds multiple functional elements within a compact volume: the tapered electrodes are nested within dielectric layers, which are in turn nested within the chip's back-end-of-line metallization stack. This nested arrangement maximizes capacitance density by efficiently utilizing vertical space and reducing lateral expansion.
3Quantity of substance
If planar MIM capacitor structure is used, then manufacturing is simple, but capacitance per unit area is low
Solution Approach 1:
The capacitor is segmented into distinct functional regions: upper electrode with tapered sidewalls, intermediate dielectric layer, lower electrode with tapered sidewalls, and fill dielectric. Each segment can be independently optimized and manufactured using standard semiconductor processes, making the increased complexity manageable while achieving superior capacitance density.
Solution Approach 2:
The patent changes geometric parameters of the electrodes from planar to tapered three-dimensional shapes. By controlling the taper angle and height parameters during fabrication, the surface area and thus capacitance density are enhanced. These parameter changes are achieved through modified deposition or etching processes that are extensions of existing manufacturing capabilities.
Data Source
AI summary
An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.