Grating and Trim Mask Lithography for Sub-45 nm Semiconductor Features
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Solution Overview
Problem
Current lithography techniques struggle to achieve the required critical dimensions and tolerances for advanced semiconductor devices, particularly bipolar transistors, as the frequency of unity power gain Fmax exceeds 200 GHz, due to limitations in reducing the width of features such as the collector implant window and emitter poly contact pedestal.
Innovation Solution
A two-step process using a grating mask to expose ultra-fine lines in a photoresist layer, followed by a trim mask to control the length of these lines, combined with the use of phase shifting masks to enhance focus and reduce mask error functions, allowing for features with approximately half the critical dimension of current binary-mask lithography techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional 248 nm deep ultraviolet lithography is used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates as Fmax exceeds 200 GHz
Solution Approach 1:
The lithography process is divided into two separate steps: first exposure through a grating mask to create periodic line patterns, and second exposure through a trim mask to refine and adjust the critical dimensions. This segmentation allows each mask to be optimized for its specific function, achieving sub-45 nm precision without requiring complete process overhaul
Solution Approach 2:
The grating mask performs preliminary patterning to establish the base critical dimensions and periodic structures. This preliminary action creates a foundation that the trim mask can then refine, allowing precise control of final dimensions while simplifying the overall process compared to implementing full precision in a single exposure step
2Manufacturing precision
If advanced lithography techniques are used, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The invention changes the parameters of conventional lithography by introducing periodic grating structures in the mask design. These gratings create interference patterns that self-align and produce precise sub-45 nm features. The trim mask further adjusts parameters like line width and spacing. This parameter-based approach achieves advanced precision using existing 248 nm equipment rather than requiring new lithography systems
3Manufacturing precision
If feature width is reduced to achieve smaller critical dimensions, then manufacturing precision improves, but ease of manufacture deteriorates
Solution Approach 1:
The manufacturing process is segmented into two exposures: grating mask exposure for establishing base patterns and periodic structures, followed by trim mask exposure for precise dimension control. This segmentation makes the complex task of sub-45 nm fabrication manageable by breaking it into two simpler, optimized steps rather than attempting single-step precision
Solution Approach 2:
The grating mask acts as an intermediary that creates periodic intermediate patterns which are then refined by the trim mask. This intermediary step translates the limitations of conventional lithography into advantages by using the grating's diffraction and interference effects to self-correct alignment errors and achieve precise sub-45 nm dimensions
4Manufacturing precision
If conventional binary-mask lithography is used, then process simplicity is maintained, but manufacturing precision deteriorates at sub-45 nm nodes
Solution Approach 1:
The invention fundamentally changes the mask design parameters from conventional binary patterns to periodic grating structures. These gratings have specific pitch, duty cycle, and phase characteristics that create interference patterns enabling sub-45 nm resolution. The trim mask adds further parameter control for precise dimension adjustment, achieving high precision while maintaining compatibility with existing process equipment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor features with resolutions as small as 50 nm, relaxing dimension and alignment requirements, increasing exposure latitude and depth of field, and reducing mask error functions, thus overcoming the limitations of conventional photolithographic techniques.
Implementation Method 1
A grating mask may then be used to expose arrays of ultra-fine lines in a photoresist layer having critical dimensions (CDs) narrower than the capability of current lithography techniques
Implementation Method 2
A second trim mask may then be applied over the array of ultra-fine lines in the photoresist layer to trim out neighboring exposed lines
Implementation Method 3
combined with the use of phase shifting masks to enhance focus and reduce mask error functions
Data Source
AI summary
Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask.