Gray-to-Binary Converter Circuit for Low-Noise CMOS Image Sensors

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Solution Overview

Problem

CMOS image sensors face challenges in high-speed operation and noise reduction during analog-to-digital conversion, particularly due to high power consumption and noise associated with electromechanical switches in existing conversion methods.

Innovation Solution

A gray code-to-binary code converter is implemented using multiple parallel-in parallel-out (PIPO) latches and a parallel-in serial-out (PISO) circuit with XOR gates and switches, which converts parallel gray code into binary code and sequentially outputs bits from least significant to most significant bit, reducing noise and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single ADC operates at high speed to convert analog pixel signals from all column lines, then the conversion speed is improved, but power consumption increases significantly

Engineering Contradiction:
Improveconversion speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides the ADC system into multiple column ADCs, each handling a specific column of pixel signals. This segmentation allows parallel processing of multiple columns simultaneously, achieving high conversion speed without requiring a single high-speed ADC that would consume excessive power. Each column ADC operates at a moderate speed, reducing individual power consumption while maintaining overall high throughput through parallel operation.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If electromechanical switches are used in the code conversion circuit, then the conversion function is achieved, but noise is generated

Engineering Contradiction:
Improveconversion functionVSAvoidnoise
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The patent replaces electromechanical switches with transistor-based switching circuits in the code conversion process. This substitution eliminates the mechanical contact noise inherent in traditional electromechanical switches while maintaining the switching functionality required for gray code to binary code conversion. The transistor-based implementation provides noise-free signal switching essential for high-quality image sensor operation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If parallel gray code is converted to parallel binary code directly, then the conversion is efficient, but noise reduction is limited

Engineering Contradiction:
Improveconversion efficiencyVSAvoidnoise
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent implements preliminary correlated double sampling (CDS) before the gray code to binary code conversion. This preliminary action captures and stores the pixel signals in a first memory, allowing subsequent subtraction of reference signals to remove noise components. By performing noise reduction before the code conversion, the system achieves both efficient parallel conversion and effective noise reduction, as the conversion operates on already-conditioned signals.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12088948B2Gray code-to-binary code converter and devices including the same
Publication Date: 2024.09.10 SAMSUNG ELECTRONICS CO LTD
  • US12088948B2 patent drawing
  • US12088948B2 patent drawing
  • US12088948B2 patent drawing

AI summary

A gray code-to-binary code converter includes multiple parallel-in parallel-out (PIPO) latches, each of the multiple PIPO latches configured to output a parallel output gray code by latching a parallel input gray code in response to a sampling signal, and a parallel-in serial-out (PISO) circuit including a first group of switches, the PISO circuit configured to convert the parallel output gray code, which is latched in the multiple PIPO latches, into a binary code, and sequentially output bits of the binary code in units of bit, from a least significant bit (LSB) of the binary code to a most significant bit (MSB) of the binary code, while changing an arrangement of the first group of switches.