Gray-Code ADC Circuit Without Clock Trimming
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Solution Overview
Problem
Conventional analog-to-digital converters require clock signals and trimming, which increases logistical effort and fabrication complexity, especially when integrated circuits need only minimal trimming beyond the clock generator, and capacitors face leakage issues.
Innovation Solution
Analog-to-digital converters operate without a clock signal using a resistor ladder and comparators, generating a Gray code representation by selectively providing reference values and the analog input signal to comparator inputs based on previous bit outputs, controlled by logic combinations like XOR gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ADCs use clock generators with trimming, then conversion accuracy is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the clock generator and trimming circuitry from the ADC system entirely. Instead of using a clocked successive approximation register approach, the invention employs an asynchronous comparator-based architecture that derives timing from the analog signal itself, eliminating the need for precision clock generation and trimming components.
Solution Approach 2:
The ADC system uses the analog input signal itself to generate the timing references needed for conversion. The signal's own characteristics (amplitude, frequency) are used to control the switching and comparison process, making the system self-regulating and eliminating external trimming requirements.
2Ease of manufacture
If ADCs operate without clock signals, then manufacturing cost is reduced, but conversion precision may deteriorate
Solution Approach 1:
The patent changes the fundamental operating parameter from fixed-clock-frequency to signal-dependent timing. The conversion process adapts its timing characteristics based on the input signal's amplitude and frequency, allowing precise conversion without requiring precision clock circuits or trimming.
Solution Approach 2:
The system transitions from static, pre-programmed timing (clock signals) to dynamic, signal-adaptive timing. The comparison and switching operations are timed based on the instantaneous characteristics of the analog signal being converted, enabling high precision without fixed-frequency clock generators.
3Device complexity
If resistor ladders are used for reference voltages, then device simplicity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates feedback mechanisms where the digital output codes are used to control the selection of reference voltages. This closed-loop approach compensates for variations in resistor values, allowing the use of standard-tolerance resistors while maintaining high conversion accuracy.
Solution Approach 2:
The resistor network serves multiple functions: it provides reference voltages for multiple comparators simultaneously, and its values are adaptively selected based on the digital output state. This multi-functionality reduces the overall precision requirements for individual resistors while maintaining system accuracy.
Data Source
Figure 1~2
Figure 3
Figure 4A~4B
AI summary
An analog-to-digital converter is provided which is configured to output an n-bit signal in response to an analog input signal. n is greater than 1. The converter comprises n comparators, where each comparator is configured to output one bit of the n-bit signal and comprising a first input and a second input. A first comparator is configured to receive the analog input signal at its first input and a reference value at its second input and to output the first, most significant bit of the n-bit signal. For the remaining comparators, an i-th comparator, i=2...n, is configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device. The i-th input device is configured to selectively provide one of 2i-1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.