Multi-Bit Gray Code Circuit Without Intermediate Logic Delays
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Solution Overview
Problem
Existing multi-bit gray code counters face limitations in increasing the frequency of gray code output due to the presence of multiple logic circuits between flip-flop circuits, which restricts the drive frequency of the clock signal and subsequent gray code generation.
Innovation Solution
A multi-bit gray code generation circuit is designed with a configuration where each gray code generation circuit consists of multiple flip-flop circuits, with outputs from previous stages inputted to subsequent stages, and the final stage's output inverted and held by the first stage, eliminating intermediate logic circuits to enhance clock signal frequency and gray code output frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic circuits are connected between flip-flop circuits to generate multi-bit gray code, then the gray code can be generated with proper logic functionality, but the delay time increases and the drive frequency cannot be increased
Solution Approach 1:
The patent extracts and removes the intermediate logic circuits from between the flip-flop circuits. By eliminating these logic circuits, the delay time is reduced and the drive frequency can be increased while still maintaining the necessary gray code generation functionality through the direct connection of flip-flop outputs to inputs.
Solution Approach 2:
The patent merges the functionality of the flip-flop circuits by directly connecting the output of one flip-flop to the input of the next, eliminating the need for separate logic circuits. This integration reduces the overall delay time and allows for higher drive frequencies while maintaining the gray code generation capability.
2Ease of manufacture
If logic circuits are placed between flip-flop circuits, then the gray code logic operations can be performed, but the frequency of the gray code output cannot be increased
Solution Approach 1:
The patent extracts the logic operation functionality from separate logic circuits and integrates it directly into the flip-flop connection structure. By removing the intermediate logic circuits, the gray code output frequency can be increased while the logic operation capability is maintained through the reconfigured direct connections.
3Reliability
If multiple logic circuits are connected between flip-flop circuits, then the gray code generation can be achieved, but the delay time increases limiting the clock signal frequency
Solution Approach 1:
The patent removes the intermediate logic circuits that cause delay time accumulation. By extracting these logic circuits from the signal path between flip-flops, the overall delay time is reduced, allowing for higher clock signal frequencies while maintaining gray code generation capability.
Solution Approach 2:
The patent reconfigures the flip-flop connections so that the necessary logic operations are performed in advance through the direct feedback and input connections, eliminating the need for subsequent logic circuit processing and reducing the overall delay time.
Data Source
AI summary
A multi-bit gray code generation circuit includes: a zeroth bit gray code generation circuit configured to generate a gray code corresponding to a bit 0 of a multi-bit gray code; and a plurality of gray code generation circuits each configured to generate a gray code corresponding to each bit higher than the bit 0 of the multi-bit gray code. Each of the plurality of gray code generation circuits is constituted by a plurality of flip-flop circuits. An output of a flip-flop circuit in the previous stage is input to a flip-flop circuit of the next stage. An output of a flip-flop circuit of the final stage is inverted and held by a flip-flop circuit of the first stage. An output of one of the plurality of flip-flop circuits is output as a gray code corresponding to each bit.