Gray Code Counter for High-Resolution A/D Conversion

Solution Overview

Problem

Conventional A/D conversion methods in solid-state image capturing apparatuses face challenges in increasing resolution without escalating area occupancy and power consumption, particularly due to limitations in gray code counter design and reference clock frequency.

Innovation Solution

The proposed A/D conversion apparatus employs a gray code counter that generates digital values using a reference clock or its reverse clock, where the most significant bits to the second least significant bit are defined as count values, and the least significant bit is generated from the reference clock or its reverse clock, allowing for increased resolution without raising the reference clock frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the reference clock frequency is increased to increase A/D conversion resolution, then the resolution is improved, but the area occupancy and power consumption of the gray code counter increase

Engineering Contradiction:

ImproveA/D conversion resolutionVSAvoidarea occupancy of gray code counter

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The gray code counter is segmented into two independent parts: (1) a counter that counts clock cycles to generate most significant bits, and (2) a separate least significant bit generation circuit that uses logic operations on clock signals. This segmentation allows the counter to operate at a lower frequency while still achieving high resolution through the combination of count value and least significant bit

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the operational parameters of the gray code counter by separating the counting function from the least significant bit generation. The counter operates at a lower frequency (counting clock cycles rather than operating at the full reference clock frequency), while the least significant bit is generated through logic operations. This parameter change resolves the contradiction by maintaining high resolution without requiring the counter to operate at high frequency

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If the reference clock frequency is increased to increase A/D conversion resolution, then the resolution is improved, but the power consumption of the gray code counter increases

Engineering Contradiction:

ImproveA/D conversion resolutionVSAvoidpower consumption of gray code counter

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The gray code counter is segmented into two independent parts: (1) a counter that counts clock cycles to generate most significant bits, and (2) a separate least significant bit generation circuit that uses logic operations on clock signals. This segmentation allows the counter to operate at a lower frequency while still achieving high resolution through the combination of count value and least significant bit

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the operational parameters of the gray code counter by separating the counting function from the least significant bit generation. The counter operates at a lower frequency (counting clock cycles rather than operating at the full reference clock frequency), while the least significant bit is generated through logic operations. This parameter change resolves the contradiction by maintaining high resolution without requiring the counter to operate at high frequency

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If the number of bits of gray code is increased to increase resolution, then the resolution is improved, but the device complexity increases

Engineering Contradiction:

ImproveresolutionVSAvoiddevice complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The invention changes the operational parameters of the gray code counter by separating the counting function from the least significant bit generation. The counter operates at a lower frequency (counting clock cycles rather than operating at the full reference clock frequency), while the least significant bit is generated through logic operations. This parameter change resolves the contradiction by maintaining high resolution without requiring the counter to operate at high frequency

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8421891B2A/D conversion apparatus using gray code counter, solid-state image capturing apparatus and electronic information device

Publication Date: 2013.04.16 SHARP KK

AI summary

An A/D conversion apparatus according to the present invention for comparing a reference signal with an analog signal, and when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided, and the A/D conversion apparatus includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.